Input Synchronization Delay - Analog Devices ADSP-2106x SHARC User Manual

11.2.3.1 Input Synchronization Delay

The ADSP-2106x has several asynchronous inputs:
CS DMAR1 DMAR2 IRQ
, , ,
inputs). These inputs can be asserted in arbitrary phase to the
processor clock, CLKIN. The ADSP-2106x synchronizes the inputs
prior to recognizing them. The delay associated with recognition is
called the synchronization delay.
Any asynchronous input must be valid prior to the recognition point
to be recognized in a particular cycle. If an input does not meet the
setup time on a given cycle, it may be recognized in the current cycle
or during the next cycle.
Therefore, to ensure recognition of an asynchronous input, it must be
asserted for at least one full processor cycle plus setup and hold time
RESET
(except for , which must be asserted for at least four processor
cycles). The minimum time prior to recognition (i.e. the setup and hold
time) is specified in the ADSP-2106x Data Sheet.
11.2.4 Interrupt & Timer Pins
The ADSP-2106x's external interrupt pins, flag pins, and timer pin can
be used to send and receive control signals to and from other devices
in the system.
Hardware interrupt signals are received on the
can come from devices that require the ADSP-2106x to perform some
task on demand. A memory-mapped peripheral, for example, can use
an interrupt to alert the processor that it has data available. Interrupts
are described in detail in the Program Sequencing chapter.
The TIMEXP output is generated by the on-chip timer. It indicates to
other devices that the programmed time period has expired. The timer
is also described in detail in the Program Sequencing chapter.
11.2.5 Flag Pins
The FLAG pins allow single-bit signalling between the ADSP-2106x
3-0
and other devices. For example, the ADSP-2106x can raise an output
flag to interrupt a host processor. Each flag pin can be programmed to
be either an input or output. In addition, many ADSP-2106x
instructions can be conditioned on a flag's input value, enabling
efficient communication and synchronization between multiple
processors or other interfaces.
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System Design
RESET
, and FLAG (when configured as
2-0 3-0
IRQ
2-0
11
TRST HBR
, , ,
pins. Interrupts
11 – 11