Master Mode Dma Operation - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

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SPI transfers. For example, the

scratch register for temporary data storage. Writing to the

When the SPI DMA engine is configured for transmitting:

1. The receive interface cannot generate an interrupt, but the status

can be polled.

2. The four-deep FIFO is not available in the receive path.

Similarly, when the SPI DMA engine is configured for receiving,

1. The transmit interface cannot generate an interrupt, but the status

can be polled.

2. The four-deep FIFO is not available in the transmit path.

Master Mode DMA Operation

To configure the SPI port for master mode DMA transfers:

1. Specify which

one or more of the

2. Enable the device as a master and configure the SPI system by

selecting the appropriate word length, transfer format, baud rate,

and so on in the

(bits 1–0) in the

or receive with DMA mode (

3. Activate the desired slaves by clearing one or more of the SPI flag

ADSP-21368 SHARC Processor Hardware Reference

Serial Peripheral Interface Ports

pins to use as the slave-select signals by setting

bits (bits 3–0) in the SPI flag (

registers is configured to select transmit

registers if

registers should not be used as a

registers. The