Sport Interrupts - Analog Devices ADSP-2106x SHARC User Manual

10 Serial Ports
10.1.1

SPORT Interrupts

Each serial port has a transmit DMA interrupt and a receive DMA
interrupt. When serial port DMA is not enabled, the interrupts occur
for each data word transmitted and received. The priority of the serial
port interrupts is shown in Table 10.2.
Interrupt
Name* Interrupt
SPR0I SPORT0 Receive DMA Channel
SPR1I SPORT1 Receive DMA Channel
SPT0I SPORT0 Transmit DMA Channel
SPT1I SPORT1 Transmit DMA Channel
Table 10.2 SPORT Interrupts
* These names are defined in the def21060.h include file supplied with the
ADSP-21000 Family Development Software.
SPORT Interrupts occur on the second system clock (CLKIN) after the
last bit of the serial word is latched in or driven out.
10.2 SPORT
There are two ways to reset the serial ports: a hardware reset using the
RESET
pin of the processor, and a software reset accomplished by
clearing the serial port's enable bit (SPEN) in the STCTLx and SRCTLx
control registers. Each method has a different effect on the serial port.
A hardware reset disables the serial ports by clearing the STCTLx and
SRCTLx control registers (including the SPEN enable bits) and the
TDIVx and RDIVx frame sync divisor registers. Any ongoing
operations are aborted.
A software reset of the SPEN enable bit(s) disables the serial port(s)
and aborts any ongoing operations. Status bits are also cleared.
The serial ports will be ready to start transmitting or receiving data
two CLKIN cycles after they are enabled (in the STCTLx or SRCTLx
control register). No serial clocks will be lost from this point on.
10 – 4
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RESET
RESET
Highest Priority
Lowest Priority