Sport Control Registers & Data Buffers - Analog Devices ADSP-2106x SHARC User Manual

10.3 SPORT CONTROL REGISTERS & DATA BUFFERS
The registers used to control and configure the serial ports are part of the
IOP register set. Each SPORT has its own set of the following control
registers and data buffers:
Register
Name* Function
STCTLx SPORT Transmit Control Register
TXx Transmit Data Buffer
TDIVx Transmit Clock & Frame Sync Divisors
MTCSx Multichannel Transmit Select
MTCCSx Multichannel Transmit Compand Select
SRCTLx SPORT Receive Control Register
RXx Receive Data Buffer
RDIVx Receive Clock & Frame Sync Divisors
MRCSx Multichannel Receive Select
MRCCSx Multichannel Receive Compand Select
SPATHx SPORT Path Length (for mesh multiprocessing)
KEYWDx SPORT Receive Comparison**
KEYMASKx SPORT Receive Comparison Mask**
* x = 0, 1
** ADSP-21061 only
Table 10.3 (on the next page) shows the memory-mapped address and
reset initialization value of each SPORT register. All of the registers are 32
bits wide, except for the 16-bit SPATHx register and location 0x00FF.
(Note that for standard, non-mesh-multiprocessing operation of the serial
ports, the SPATHx register and location 0x00FF must remain equal to the
reset initialization value, 0x0001.)
The SPORT control registers are programmed by writing to the
appropriate address in memory. The symbolic names of the registers and
individual control bits can be used in ADSP-2106x programs—the
#define definitions for these symbols are contained in the file
def21060.h which is provided in the INCLUDE directory of the ADSP-
21000 Family Development Software. The def21060.h file is shown in
the Control/Status Registers appendix of this manual. All control and status
bits in the SPORT registers are active high unless otherwise noted.
Because the SPORT registers are memory-mapped they cannot be written
with data coming directly from memory. They must instead be written
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Serial Ports 10
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