Active Low Versus Active High Frame Syncs; Sampling Edge For Data And Frame Syncs - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

Hide thumbs Also See for SHARC ADSP-21368:

Table of Contents

Active Low Versus Active High Frame Syncs

Frame sync signals may be active high or active low (for example,

inverted). The

the frame sync's logic level:

active high.

Active high frame syncs are the default. The

after a processor reset.

Data and frame syncs can be sampled on the rising or falling edges of the

SPORT clock signals. The

the sampling edge.

For sampling receive data and frame syncs, setting

registers selects the rising edge of

the processor selects the falling edge of

data and frame syncs. Note that transmit data and frame sync signals

change their state on the clock edge that is not selected.

For example, the transmit and receive functions of any two SPORTs con-

nected together should always select the same value for

internally-generated signals are driven on one edge and received signals are

sampled on the opposite edge.

ADSP-21368 SHARC Processor Hardware Reference

bit (bit 16) of the

is cleared (=0), the corresponding frame sync signal is

is set (=1), the corresponding frame sync signal is active

control registers determines

bit is initialized to zero

control registers selects

for sampling receive

Serial Ports

is cleared (=0),

Do you have a question about the SHARC ADSP-21368 and is the answer not in the manual?