Figure 3.5 Delayed Branches - Analog Devices ADSP-2106x SHARC User Manual

Program Sequencing
In a delayed branch, the processor continues to execute two more
instructions while the instruction at the branch address is fetched and
decoded (see Figure 3.5); in the case of a call, the return address is the
third address after the branch instruction. A delayed branch is more
efficient, but it makes the code harder to understand because of the
instructions between the branch instruction and the actual branch.
DELAYED JUMP OR CALL
CLOCK CYCLES
Execute
n
Instruction
Decode
n+1
Instruction
Fetch
n+2
Instruction
DELAYED RETURN
CLOCK CYCLES
Execute
n
Instruction
Decode
n+1
Instruction
Fetch
n+2
Instruction
n = Branch instruction
j = Instruction at Jump or Call address
r = Instruction at Return address

Figure 3.5 Delayed Branches

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n+1 n+2
n+2
j j+1
for call, n+3
pushed on PC
stack
n+1 n+2
n+2 r
r r+1
r popped from
PC stack
3
j
j j+1
j+2
r
r+1
r+2
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