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Instruction Pipeline
The program sequencer determines the next instruction address by exam-
ining both the current instruction being executed and the current state of
the processor. If no conditions require otherwise, the processor executes
instructions from memory in sequential order by incrementing the look-
ahead address.
The processor has a ten-stage instruction pipeline, shown in
Table 4-2. Stages of Instruction Pipeline
Pipeline Stage
Instruction Fetch 1 (IF1)
Instruction Fetch 2 (IF2)
Instruction Fetch 3 (IF3)
Instruction Decode (DEC)
Address Calculation (AC)
Data Fetch 1 (DF1)
Data Fetch 2 (DF2)
Execute 1 (EX1)
Execute 2 (EX2)
Write Back (WB)
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Description
Issue instruction address to IAB bus, start compare tag of
instruction cache
Wait for instruction data
Read from IDB bus and align instruction
Decode instructions
Calculation of data addresses and branch target address
Issue data address to DA0 and DA1 bus, start compare tag of
data cache
Read register files
Read data from LD0 and LD1 bus, start multiply and video
instructions
Execute/Complete instructions (shift, add, logic, etc.)
Writes back to register files, SD bus, and pointer updates (also
referred to as the "commit" stage)
Program Sequencer
Table
4-2.
4-7
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