I2C Multimaster Peripheral
Transmitter/Receiver Mode (TRX)
2
Table 29. I
C Controller Transmitter/Receiver Operating Modes
Expand Address (XA)
80
Serial Interfaces
Master mode only.
When this bit is cleared, the I
data line SDA is shifted into the receiver FIFO and can be read from the
I2C_DATA register.
When this bit is set, the I
written in the transmitter FIFO via I2C_DATA is shifted out on data line SDA.
0: Receiver mode
-
1: Transmitter mode
-
Value after reset is low. The operating modes are defined as shown in
Table 29.
MST
0
0
1
1
When set, this bit expands the address to 10-bit.
0: 7-bit address mode
-
1: 10-bit address mode
-
Value after reset is low.
2
C controller is in the receiver mode, and data on
2
C controller is in the transmitter mode, and the data
TRX
Operating Modes
x
Slave receiver
x
Slave transmitter
0
Master receiver
1
Master transmitter
SPRU760B