Scl Low Time (Scll) - Texas Instruments OMAP5912 Reference Manual

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Table 34. I C SCL Low Time Control Register(I2C_SCLL)
Bit Name
15:8 −
7:0 SCLL

SCL Low Time (SCLL)

2
Table 35. I C SCL High Time Control Register(I2C_SCLH)
Bit Name
15:8 −
7:0 SCLH
SPRU760B
0x0: Divide by 1
0x1: Divide by 2
↓ ↓
0xFF: Divide by 256
Values after reset are low (all 8 bits).
Description
Reserved
SCL low time
This register determines the SCL low time value when master.
Master mode only.
This 8-bit value generates the SCL low time value (t
is operated in master mode.
The SCL low time depends on the I2C_PSC value and the ICLK time period
(internal sampling clock rate):
When I2C_PSC = 0, t
-
When I2C_PSC = 1, t
-
When I2C_PSC > 1, t
-
The different values to compute the SCL low time are due to the
synchronization stage and noise filter on the SCL line.
Values after reset are low (all 8 bits).
Description
Reserved
SCL high time
This register determines the SCL high time value when master.
= (SCLL+7) * ICLK time period
LOW
= (SCLL+6) * ICLK time period
LOW
= (SCLL+5) * ICLK time period
LOW
I2C Multimaster Peripheral
) when the peripheral
LOW
Serial Interfaces 83