Texas Instruments OMAP5912 Reference Manual page 52

OMAP5912 Description
Boot Device Configuration
Boot ROM
Security Layer
Generic Distributed DMA (GDD)
52 Introduction
The electrical fuse cell contains an electrically programmable element whose
output can be permanently set to logic 1 instead of its natural unprogrammed
state, logic 0.
The MPU can access the die ID and the production ID through an MPU
peripheral access.
Depending on the device_type signal, the MPU core can boot either from the
flash or from the boot ROM. The C55x DSP core can boot either from internal
memory or from external memory. The boot is accomplished with an
orderlycombination of hardware and software control sequences.
-
MPU boot ROM
Upon the deassertion of the reset input pin (cold reset exit) of OMAP 3.2,
ARM926EJS traps to its reset vector, while the C55x DSP is held in reset.
-
DSP boot modes
System software controls the C55x DSP boot option by programming
registers via the MPUI interface when the DSP is being held in reset.
The OMAP5912 configuration is 16384 x 32 bits. For more detail, see Chapter
5, Initialization.
The OMAP 3.2 gigacell includes special-purpose security hardware that is
used to activate a secure mode. The secure mode can be viewed as a third
privilege level on the MPU. It is used to create an environment for protecting
sensitive information from access by untrusted software. The secure mode is
set with the assertion of a dedicated signal (secure bit) that propagates across
OMAP5912 and creates a boundary between resources that trusted software
might access and those available to any software.
The GDD is a module that interfaces one OCP target device (the peripheral
target) to another OCP target device (the memory target) by providing a DMA
service to the peripheral target. The DMA service is configured through a
configuration port. GDD wraps a peripheral OCP host interface and presents
the system with one initiator and one target port.
The GDD is attached to the SSI peripheral. It provides the necessary
bandwidth between the SSI and the host without affecting the peripheral
subsystem bandwidth.
SPRU748A