Interrupt Mask Pointer Register (Imaskp - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

Interrupt Registers

Interrupt Mask Pointer Register (IMASKP)

The register is a non-memory-mapped, universal, system register
IMASKP
( and
Ureg Sreg
in the register corresponds to a bit with the same name in the
IMASKP
registers. The
IRPTL
Figure B-3 and
This register supports an interrupt nesting scheme that lets higher priority
events interrupt an interrupt service routine (ISR) and keeps lower prior-
ity events from interrupting.
When interrupt nesting is enabled, the bits in the
interrupts with lower priorities than the interrupt that is currently being
serviced. Other bits in this register unmask interrupts having higher prior-
ity than the interrupt that is currently being serviced. Interrupt nesting is
enabled using
lower priority interrupt even when masked, and the processor responds to
that latched interrupt if it is later unmasked.
When interrupt nesting is disabled (
bits in the
IMASKP
rently being serviced. The
when masked, and the processor responds to the highest priority latched
interrupt after servicing the current interrupt.
B-22
). The reset value for this register is 0x0000 0000. Each bit
register field descriptions are shown in
IMASKP
Figure B-4 and described in
in the
NESTM MODE1
register mask all interrupts while an interrupt is cur-
IRPTL
ADSP-21368 SHARC Processor Hardware Reference
Table B-7.
IMASKP
register. The
IRPTL
= 0 in the
NESTM
register still latches these interrupts even
register mask
register latches a
register), the
MODE1