32-Bit Spi Host Boot - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

For 16-bit SPI devices, two words shift into the 32-bit receive shift regis-
ter ( ) before a DMA transfer to internal memory occurs. For 8-bit SPI
RXSR
devices, four words shift into the 32-bit receive shift register before a
DMA transfer to internal memory occurs.
When booting, the ADSP-21367/8/9 and ADSP-2137x processors expect
to receive words into the
are received continuously without breaks.
Operation Using the Core" on page 6-13.
processor expects to receive instructions and data packed in a least signifi-
cant word (LSW) format.
Figure 14-12 shows how a pair of instructions are packed for SPI booting
using a 32-, 16-, and an 8-bit device. These two instructions are received
as three 32-bit words as illustrated in
33445566
32-BIT HOST
5566
16-BIT HOST
8-BIT HOST
66 55
t=0
Figure 14-12. Instruction Packing for Different Hosts
The following sections examine how data is packed into internal memory
during SPI booting for SPI devices with widths of 32, 16, or 8 bits.

32-Bit SPI Host Boot

Figure 14-13 shows 32-bit SPI host packing of 48-bit instructions exe-
cuted at PM addresses 0x90000 and 0x90001. The 32-bit word is shifted
to internal program memory during the 256-word kernel load.
ADSP-21368 SHARC Processor Hardware Reference
register seamlessly. This means that bits
RXSPI
WORDS
CCDD1122
3344 1122 CCDD
44 33 22 11 DD CC BB AA
For more information, see "SPI
For different SPI host sizes, the
Figure 14-11.
INSTRUCTIONS IN
7788AABB
INTERNAL MEMORY
AABB 7788
[0x80000] 0x1122 33445566
[0x80001] 0x7788 AABBCCDD
88 77
t=96 SPICLK
System Design
14-43