Fifo Control And Status - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

FIFO Control and Status

Several bits can be used to control and monitor FIFO operations:
• IDP Enable. The
enables the IDP. This is a global control bit. This bit and the corre-
sponding IDP channel enable bit (
register must be set for data from a channel to get into the FIFO.
• IDP Buffer Hang Disable. The
register) determines whether or not the core hangs on reads when
the FIFO is empty.
• Number of Samples in FIFO. The
the
DAI_STAT
the FIFO.
• FIFO Overflow Status. The
monitor the overflow error conditions in the FIFO for each of the
channels.
• FIFO Overflow Clear. The
register) clears an indicated FIFO overflow error.
To enable the IDP, two separate bits in two different registers must be set.
The first is the
the specific channel enable bit which is located in the
When these bits are set (= 1), the IDP is enabled. When these bits are
cleared (= 0), the IDP is disabled, and data cannot come to the
register from the IDP channels. When the
1 to 0, all data in the IDP FIFO is cleared. Writing a 1 to bit 31 of the
register also clears the FIFO. This is a write-only bit and always
IDP_CTL1
returns a zero on reads.
The bit is used for buffer hang disable control. When there is no
IDP_BHD
data in the FIFO, reading the
This condition continues until the FIFO contains valid data. Setting the
ADSP-21368 SHARC Processor Hardware Reference
IDP_ENABLE
register) monitor the number of valid data words in
bit in the
IDP_ENABLE
IDP_FIFO
bit (bit 7 of the
) in the
IDP_ENx
bit (bit 4 in the
IDP_BHD
IDP_FIFOSZ
bits in the
SRU_OVFx
bit (bit 6 of the
IDP_CLROVR
register and the second is
IDP_CTL0
IDP_ENABLE
register causes the core to hang.
Input Data Port
register)
IDP_CTL0
IDP_CTL1
IDP_CTL0
bits (bits 31–28 in
register
DAI_STAT
IDP_CTL0
register.
IDP_CTL1
IDP_FIFO
bit transitions from
7-15