Transmit & Receive Data Buffers (Tx, Rx) - Analog Devices ADSP-2106x SHARC User Manual

After a write to a SPORT register, control and mode bit changes
generally take effect in the second CLKIN cycle after the write is
completed. The serial ports will be ready to start transmitting or
receiving two CLKIN cycles after they are enabled (in the STCTLx or
SRCTLx control register). No serial clocks will be lost from this point
on.
10.3.2 Transmit & Receive Data Buffers (TX, RX)
TX0 and TX1 are the transmit data buffers for SPORT0 and SPORT1.
They are 32-bit buffers which must be loaded with the data to be
transmitted; the data is loaded either by the DMA controller or by the
program running on the ADSP-2106x core. RX0 and RX1 are the
receive data buffers for SPORT0 and SPORT1. They are 32-bit buffers
which are automatically loaded from the receive shifter when a
complete word has been received. Word lengths of less than 32 bits are
right-justified in the receive and transmit buffers.
The TX buffers act like a two-location FIFO because they have a data
register plus an output shift register (see Figure 10.1); two 32-bit words
may be stored in TX at any one time. When the TX buffer is loaded and
any previous word has been transmitted, the buffer contents are
automatically loaded into the output shifter. An interrupt is generated
when the output shifter has been loaded, signifying that the TX buffer
is ready to accept the next word (i.e. the TX buffer is "not full"). This
interrupt will not occur if serial port DMA is enabled or if the
corresponding mask bit in the IMASK register is set.
The transmit underflow status bit (TUVF) will be set in the transmit
control register when a transmit frame synch occurs and no new data
has been loaded into TX. The TUVF status bit is "sticky" and is only
cleared by disabling the serial port.
The RX buffers act like a three-location FIFO because they have two
data registers plus an input shift register. Two complete 32-bit words
can be stored in RX while a third word is being shifted in. The third
word will overwrite the second if the first word has not been read out
(by the ADSP-2106x core or the DMA controller). When this happens,
the receive overflow status bit (ROVF) will be set in the receive control
register. Almost three complete words can be received without the RX
buffer being read before overflow occurs. The overflow status is
generated on the last bit of third word. The ROVF status bit is "sticky"
and is only cleared by disabling the serial port.
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Serial Ports 10
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