Texas Instruments OMAP5912 Reference Manual page 26

OMAP5912 Description
26 Introduction
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TMS320C55xt (C55xt) DSP including:
J
Embedded ICE emulator interface through JTAG port
J
C55xt DSP rev 2.11
J
L1 cache (24K bytes)
H
16K-byte, two-way set-associative instruction cache
H
2x 4K-byte RAM set for instruction
J
DARAM 64K-byte, zero wait state, 32-bit organization
J
SARAM 96K-byte, zero wait state, 32-bit organization
J
PDROM (32K bytes)
J
DMA controller: 6 physical channels, 5 ports
J
DSP trace module
J
Hardware accelerators motion estimation (ME), discrete/inverse
discrete cosine transform (DCT/IDCT) and pixel interpolation (PI)
J
DSP level 1 interrupt handler in the C55xt DSP core
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DSP MMU
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DSP level 2 interrupt handler, which enables connection to 16 additional
interrupt lines outside OMAP. The priority of each interrupt line is
controlled by software.
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DSP interrupt interface, which enables connection to the interrupt lines
coming out of the level 2 interrupt handler and the interrupt lines requiring
more priority. The outcome interrupt of this module is then connected to
the C55x DSP to be processed. This module is mainly used to ensure that
all interrupts going to the DSP are level-sensitive.
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DSP peripherals:
J
3x 16-bit DSP private timers
J
1x 16-bit DSP private watchdog
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Mailboxes:
J
Four mailboxes are implemented:
H
Two read/write accessible by MPU, read-only by the DSP
H
Two read/write accessible by the DSP, read-only by the MPU
Each mailbox is implemented with 2x 16-bit registers. When a write
is done into a register by one processor, it generates an interrupt,
released by the read access of the other processor.
SPRU748A