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Figure 28.
Master Transmitter Mode, Interrupt
Read I
No
Write I
Read I
ACK returned
STT and STP are
cleared to 0 by hardware.
the registers.
SPRU760B
[EXPECTED COMMAND]
Start
At the beginning,
(STT,STP) = (1.0), (1.1)
2
C_STAT.
in the middle,
(STT, STP) = (0.0), (0.1)
At the end,
Is
(STT, STP) = (0.1)
bus free
(BB = 0)
2
[EXPECTED I
?
2
I
C_IE = 11111b
Yes
Set appropriate values to every
2
C_CON
2
bit of I
C_CON. I
with 8603h.
2
to 1 to take I
C out of reset condition. Setting
2
I
C_EN and setting other mode bits can be done
simultaneously.
Is
No
interrupt
received
?
Yes
2
C_STAT.
Is
Yes
(NACK = 0)
?
No
Reprogram
STT = 1
No
STP = 1
(new start)
?
?
Yes
Yes
End
C_IE]
2
C_EN bit must be set
Are
n bytes
No
transferred
(ARDY = 1)
?
Yes
No
2
The I
C goes into slave receiver mode.
I2C Multimaster Peripheral
Is
send data
No
being requested
(XRDY = 1)
?
Yes
2
Write I
C_DATA.
2
Write I
C_STAT
(clear XRDY)
Serial Interfaces
93
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