Texas Instruments OMAP5912 Reference Manual page 15

1.1 Subsystems
SPRU748A
The OMAP5912 chip subsystems have these characteristics:
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The MPU subsystem is based on the ARM926EJ core, which performs
most operations on the chip.
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The DSP subsystem is based on a TMS320C55xt DSP core, which
performs intensive data computing tasks.
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The internal memory subsystem (frame buffer) is a single-port SRAM .
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The system DMA helps the MPU perform data memory transfer-specific
tasks, leaving a million more instructions available per second (MIPS) for
both processors.
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The system components (ULPD, oscillators, etc.) are responsible for
managing system interactions, such as interrupt, clock control, and idle.
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The memory interfaces define the system memory access organization of
OMAP5912.
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The peripheral subsystem defines all of the components used to interface
OMAP5912 with specific external devices, such as compact camera port
(CCP), keyboard, and smart display.
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The security modules include ROM, a single port SRAM, eFuse cells, and
secure peripherals, which enable the system to support secure
applications.
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The universal serial bus (USB) and synchronous serial interconnect (SSI)
interface enable the platform to support a universal serial link and a
dedicated modem interface, which in turn enable a high data transfer rate
between the modem and the OMAP5912.
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The device features two types of interconnectivity:
J
The L3 interconnect is the memory interconnection among the MPU,
DSP, DMA, and an external host (through USB or SSI interface).
J
The L4 interconnect provides all of the peripheral interconnections
among the MPU, DSP, and DMA.
Overview
Introduction 15