Jtag Emulator Cable Pod Signal Timing; Jtag Emulator Cable Pod Timing Diagram; Emulator Cable Pod Timing Parameters - Texas Instruments TMS320C6000 Reference Manual

5

JTAG Emulator Cable Pod Signal Timing

Figure 3 shows the signal timings for the emulator cable pod. Table 2 defines
the timing parameters. These timing parameters are calculated from values
specified in the standard data sheets for the emulator and cable pod and are
for reference only. Texas Instruments does not test or guarantee these timings.
The emulator pod uses TCK_RET as its clock source for internal synchroni-
zation. TCK is provided as an optional target system test clock source.
Figure 3.

JTAG Emulator Cable Pod Timing Diagram

TCK_RET
TMS/TDI
TDO
Table 2.

Emulator Cable Pod Timing Parameters

No. Reference Description
1 t TCK_RET period
c(TCK)
2 t TCK_RET high-pulse duration
w(TCKH)
3 t TCK_RET low-pulse duration
w(TCKL)
4 t Delay time, TMS/TDI valid from TCK_RET low
d(TMS)
5 t TDO setup time to TCK_RET high
su(TDO)
6 t TDO hold time from TCK_RET high
h(TDO)
SPRU641
JTAG Emulator Cable Pod Signal Timing
1
2
3
4
5
Designing for JTAG Emulation
1.5 V
6
Min Max Units
35 200 ns
15 ns
15 ns
6 20 ns
3 ns
12 ns
7