Camera Isp Sync Mode Clock Gating; Camera Isp Jpeg Stream Timing Diagrams - Texas Instruments OMAP36 Series Technical Reference Manual

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4 pulses
before start
of frame
required
cam_pclk
cam_hs
cam_vs
cam_fld
cam_d
0 3
1 2
cam_vs must be
active for at
least one clock
pulse to qualify
start of frame
6.2.4.2 Camera ISP Parallel Generic Configuration: JPEG Sensor Connection on the Parallel Interface
Some camera modules integrate an image-signal processor (ISP) and a JPEG encoder. The CCDC can
interface with these camera modules and transfer the received JPEG stream to memory.
To use this mode, set the
Figure 6-5 shows timing diagrams for an JPEG stream.
cam_vs
cam_hs
cam_pclk
cam_d
VS
WEN
HS
PCLK
The bridge cannot be used for JPEG sensor connections.
6.2.4.3 Camera ISP ITU-R BT.656 Protocol and Data Formats (8, 10 Bits)
The ITU-R BT.656 mode cannot be used when the bridge is enabled.
The camera ISP interface supports data in ITU-R BT.656 format.
SWPU177N – December 2009 – Revised November 2010
Public Version
Figure 6-4. Camera ISP SYNC Mode Clock Gating
4 5 6 0 3
1 2
cam_hs must be
Data sampled on rising
inactive for at
edge in this diagram.
least one clock
Programmable see
pulse between
register manual section.
2 lines
ISP_CTRL [30] JPEG_FLUSH bit.
Figure 6-5. Camera ISP JPEG Stream Timing Diagrams
Timing of JPEG compressed data in free running clock mode
Copyright © 2009–2010, Texas Instruments Incorporated
Extra pulses
allowed but not
required during
blanking
4 5 6 0
1 2
cam_hs must be
active for at
least one clock
pulse to qualify
start of line
CAUTION
CAUTION
Camera ISP Environment
8 pulses after
end of frame
Extra pulses
required between frames
allowed but not
3 4 5 6
camisp-100
Camera Image Signal Processor
required
camisp-132
1097