Spi 3-Pin Master Mode With Wdelay; Timing Diagrams - Texas Instruments AM1808 Technical Reference Manual

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29.2.20 Timing Diagrams

This section contains timing diagrams illustrating the C2TDELAY, C2EDELAY, T2CDELAY, T2EDELAY,
and WDELAY delays and their interaction with the SPIx_SCS[n] and SPIx_ENA pins for all SPI modes.
29.2.20.1 SPI 3-Pin Mode
Figure 29-13 illustrates the WDELAY option in SPI 3-pin master mode. This is the only delay available in
this mode. In CASE1, a new transfer is initiated during the WDELAY period and the transfer begins
immediately after the WDELAY period ends. In CASE2, while WDELAY has completed, a new transfer will
not begin until SPIDAT0/SPIDAT1 have been written with new data.
Case 1
(i)
SPIx_CLK
(ii)
SPIx_CLK
(iii)
SPIx_CLK
(iv)
SPIx_CLK
Case 2
(i)
SPIx_CLK
(ii)
SPIx_CLK
(iii)
SPIx_CLK
(iv)
SPIx_CLK
SPRUH82C – April 2013 – Revised September 2016
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Figure 29-13. SPI 3-Pin Master Mode with WDELAY
a
(WDELAY)
a
(WDELAY)
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Architecture
Serial Peripheral Interface (SPI)
1435