Power-Up Timing Diagram; Eeprom Configuration For Tps65910 - Texas Instruments TPS65910 User Manual

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PWRON button
VDD_RTC/ VRTC 1.8 V
CLK32KOUT TPS65910 internal clock
VDIG1
VDD1
VDD2
VIO
VDIG2
VAUX33
VMMC
VAUX1
VAUX2
VDAC
VPLL
Event:
Time slot (2 ms between slot):
Event description:
Note: PWRON press must be maintained until PWRHOLD acknowledge, or, for shorter PWRON press,
Register
VDD1_OP_REG
VDD1_REG
EEPROM
DCDCCTRL_REG
VDD2_OP_REG /
VDD2_SR_REG
VDD2_REG
EEPROM
DCDCCTRL_REG
VIO_REG
EEPROM
DCDCCTRL_REG
EEPROM
VDIG1_REG
EEPROM
VDIG2_REG
EEPROM
VDAC_REG
EEPROM
SWCU071B – December 2010 – Revised October 2015
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1.2 V
1 2 3
0 1
1 PWRON button press falling edge
2 Valid press after debounce
3 First step of power-up sequence available for DCDC, LDO activation. Time slot 0 is for internal use.
PWRHOLD must go high within 984 ms of valid PWRON press (event 2). To ensure this, PWRHOLD is tied to VIO.
Figure 3. Power-Up Timing Diagram
Table 4. EEPROM Configuration for TPS65910
Bit
SEL VDD1 voltage level selection for boot
VGAIN_SEL VDD1 gain selection, x1 or x2
VDD1 time slot selection
VDD1_PSKIP VDD1 pulse skip mode enable
SEL VDD2 voltage level selection for boot
VGAIN_SEL VDD2 gain selection, x1 or x3
VDD2 time slot selection
VDD2_PSKIP VDD2 pulse skip mode enable
SEL VIO voltage selection
VIO time slot selection
VIO_PSKIP VIO pulse skip mode enable
VDD3 time slot
SEL LDO voltage selection
LDO time slot
SEL LDO voltage selection
LDO time slot
SEL LDO voltage selection
LDO time slot
TPS65910 User Guide For OMAPL-137, OMAPL-138, and TMS320C674x
Copyright © 2010–2015, Texas Instruments Incorporated
1.2 V
1.2 V
1.8 V
1.2 V
3.3 V
3.3 V
2 3 4 5
Description
Power-Up Sequencing
32 kHz released to processor
3.3 V
3.3 V
1.8 V
1.8 V
6 7
SWCU071-003
Option Selected
1.2 V
x1
2
Skip enabled
1.2 V
x1
3
Skip enabled
1.8 V
4
Skip enabled
OFF
1.2
1
1.2 V
4
1.8 V
7
Family of Processors
9