Clock Operation Status Control Register (Csc) - Renesas RL78/G1P Hardware User Manual

RL78/G1P

5.3.3 Clock operation status control register (CSC)

This register is used to control the operations of the high-speed system clock and high-speed on-chip oscillator clock
(except the low-speed on-chip oscillator clock).
The CSC register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to C0H.
Figure 5-4. Format of Clock Operation Status Control Register (CSC)
Address: FFFA1H
Symbol <7>
CSC MSTOP
MSTOP
0
1
HIOSTOP
0
1
Cautions 1. After reset release, set the clock operation mode control register (CMC) before
Table 5-2. Preconditions for Stopping Clock Oscillation and Flag Settings
Clock
X1 clock
External main system
clock
High-speed on-chip
oscillator clock
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
After reset: C0H R/W
6 5
0 0
X1 oscillation mode
X1 oscillator operating
X1 oscillator stopped
High-speed on-chip oscillator clock operation control
High-speed on-chip oscillator operating
High-speed on-chip oscillator stopped
setting the CSC register.
2. Set the oscillation stabilization time select register (OSTS) before setting the MSTOP
bit to 0 after releasing reset. Note that if the OSTS register is being used with its
default settings, the OSTS register is not required to be set here.
3. To start X1 oscillation as set by the MSTOP bit, check the oscillation stabilization
time of the X1 clock by using the oscillation stabilization time counter status register
(OSTC).
4. Do not stop the clock selected for the CPU peripheral hardware clock (f
OSC register.
5. The preconditions for stopping oscillation of the various clocks (and for disabling
the external clock inputs) and the flag settings to be made to stop oscillation of each
clock or disable input of the given clock are listed in Table 5-2.
Before stopping the oscillation of a clock, check that the precondition for stopping
clock oscillation is satisfied.
Precondition for Stopping Clock Oscillation
(or Disabling External Clock Input)
CPU and peripheral hardware clocks operate with a clock
other than the high-speed system clock.
(MCS = 0)
CPU and peripheral hardware clocks operate with a clock
other than the high-speed on-chip oscillator clock.
(MCS = 1)
4 3
0 0
High-speed system clock operation control
External clock input mode
External clock from EXCLK
pin is valid
External clock from EXCLK
pin is invalid
CHAPTER 5 CLOCK GENERATOR
2 1
0 0 HIOSTOP
Input port mode
Input port
Flag Settings of
CSC Register
MSTOP = 1
HIOSTOP = 1
<0>
) with the
CLK
102