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IVA2.2 Subsystem Memory Space Mapping
Table 2-9. DSP View of the IVA2.2 Subsystem Memory Space
Region Name
Reserved
L2 ROM
Reserved
L2 RAM
L2 RAM (cache)
Reserved
L1P RAM (cache)
Reserved
L1D RAM
L1D RAM (cache)
Reserved
C64x+ interrupt selector
C64x+ PDC
C64x+ protection ID
C64x+ revision ID
Reserved
C64x+ EMC
Reserved
C64x+ memory system
Reserved
TPCC configuration
TPTC0 configuration
TPTC1 configuration
Reserved
SYSC configuration
WUGEN configuration
Reserved
Reserved
(1)
L2 ROM
Reserved
(1)
L2 RAM
(1)
L2 RAM (cache)
Reserved
(1)
L1P RAM (cache)
Reserved
(1)
L1D RAM
(1)
L1D RAM (cache)2
Reserved
(2)
Memories and peripherals
(1)
IVA2.2 internal memories are reachable in the [0x007E 0000-0x00F1 7FFF] and [0x107E 0000-0x10F1 7FFF] (aliasing) ranges.
(2)
For more information, see
Chapter
222
Memory Mapping
Public Version
Start Address
End Address
(Hex)
0x0000 0000
0x007D FFFF
0x007E 0000
0x007E 3FFF
0x007E 4000
0x007F 7FFF
0x007F 8000
0x007F FFFF
0x0080 0000
0x0080 FFFF
0x0081 0000
0x00DF FFFF
0x00E0 0000
0x00E0 7FFF
0x00E0 8000
0x00F0 3FFF
0x00F0 4000
0x00F0 FFFF
0x00F1 0000
0x00F1 7FFF
0x00F1 8000
0x017F FFFF
0x0180 0000
0x0180 FFFF
0x0181 0000
0x0181 0FFF
0x0181 1000
0x0181 1FFF
0x0181 2000
0x0181 2FFF
0x0181 3000
0x0181 FFFF
0x0182 0000
0x0182 FFFF
0x0183 0000
0x0183 FFFF
0x0184 0000
0x0184 FFFF
0x0185 0000
0x01BF FFFF
0x01C0 0000
0x01C0 FFFF
0x01C1 0000
0x01C1 03FF
0x01C1 0400
0x01C1 07FF
0x01C1 0800
0x01C1 FFFF
0x01C2 0000
0x01C2 0FFF
0x01C2 1000
0x01C2 1FFF
0x01C2 2000
0x0FFF FFFF
0x1000 0000
0x107D FFFF
0x107E 0000
0x107E 3FFF
0x107E 4000
0x107F 7FFF
0x107F 8000
0x107F FFFF
0x1080 0000
0x1080 FFFF
0x1081 0000
0x10DF FFFF
0x10E0 0000
0x10E0 7FFF
0x10E0 8000
0x10F0 3FFF
0x10F0 4000
0x10F0 FFFF
0x10F1 0000
0x10F1 7FFF
0x10F1 8000
0x10FF FFFF
0x1100 0000
0xFFFF FFFF
5, IVA2.2 Subsystem.
Copyright © 2009–2010, Texas Instruments Incorporated
Size (KB)
(Hex)
8064
16
80
32
64
6080
32
1008
48
32
9120
64
4
4
4
52
64
64
64
3776
64
1
1
62
4
4
233,336
8064
16
80
32
64
6080
32
1008
48
32
928
3,915,776
SWPU177N – December 2009 – Revised November 2010
www.ti.com
Description
Reserved
IVA2.2 internal memories
Reserved
IVA2.2 internal memories
IVA2.2 internal memories
Reserved
IVA2.2 internal memories
Reserved
IVA2.2 internal memories
IVA2.2 internal memories
Reserved
C64x+ DSP interrupt controller
C64x+ DSP power-down
controller
C64x+ DSP protection ID
C64x+ DSP revision ID
Reserved
C64x+ DSP extended memory
controller
Reserved
Memory controller control
registers
Reserved
DMA transfer engine control
registers
DMA transfer scheduler 0 control
registers
DMA transfer scheduler 1 control
registers
Reserved
SYSC module control registers
Wake-up generator control
registers
Reserved
Reserved
IVA2.2 internal memories
Reserved
IVA2.2 internal memories
IVA2.2 internal memories
Reserved
IVA2.2 internal memories
Reserved
IVA2.2 internal memories
IVA2.2 internal memories
Reserved
Controlled by the IVA2.2 MMU to
access memories and
peripherals external to the IVA2.2
subsystem
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