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Alternatively, a 32.768-kHz clock output from MSPM0G3507 device can be provided to the MSP430FR4131
using a GPIO output.
3.6 Direct Memory Access (DMA)
The DMA module transfers packets between the MSPM0G3507 MCU and ADS131M08 device with minimal
hardware resources and timing overhead. Two DMA channels are used for communicating to the ADS131M08.
DMA Channel 0 is used to send data to the ADS131M08 and DMA Channel 1 is used simultaneously to
receive the measurements data from the ADS131M08 over SPI bus. Once a complete packet has been received
from the ADS131M08, an interrupt is generated to complete the (optional but strongly recommended) CRC16
verification of the data packet and finally the packet disassembly into voltage and current values per each phase
line and the neutral line is done.
MSPM0G3507 MCU.
3.7 ADC Setup
The ADS131M08 registers must be initialized to deliver measurement data from all 7 channels (the 8-th channel
is unused but still has to be read out over SPI). This process is followed when the ADS131M08 is being first
setup after the MSPM0G3507 MCU resets as well as each time calibration is performed.
Figure 3-1. ADC Initialization and Synchronization Process
The SPI module of the MSPM0+ MCU is configured for communication to the ADS131M08 device as a controller
device that uses 4-wire mode (the chip-select signal is automatically asserted high and low by the SPI hardware
module) and has a 19.87-MHz SPI clock that is derived from the MCU MCLK clock, divided by 4. After the SPI
is setup, all interrupts are disabled and a reset command is sent from the MSPM0+ MCU to the ADS131M08 via
SPI. Interrupts are then re-enabled and the MSPM0+ MCU sends commands to the ADS131M08 to configure
the registers.
By sending write commands to the ADS131M08 registers, the following configuration is done:
•
MODE register settings: 16-bit CCITT CRC used, 24-bit length for each word in the ADS131M08 packet,
DRDY signal asserted on most lagging enabled channel, DRDY asserted high when conversion value is not
available, DRDY asserted low when conversion values are ready
•
GAIN1 register settings: PGA gain of 1 used for all four ADC channels
•
CFG register settings: Current detection mode disabled
•
CHx_CNG register settings (where x is the channel number)
– 3-phase mode: All seven ADC channel inputs connected to external ADC pins and channel phase delay
set to 0 for each channel (note that software phase compensation is used instead of ADS131M08
hardware phase compensation).
TIDUF25 – JUNE 2023
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Figure 3-5
shows the packets that are sent and received using the DMA of the
Setup ADS131M08 SPI
Disable IRQ
Send ADS131M08 reset pulse
Enable IRQ
Send commands to configure
ADS131M08 registers
Setup port interrupt on falling edge
of ADS131M08 DRDY
Return
ADS131M08 Setup
Copyright © 2023 Texas Instruments Incorporated
Cost-Effective, 3-Phase CT Electricity Meter Reference Design Using
System Design Theory
17
Standalone ADC
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