Gptm Timer B Match (Gptmtbmatchr) Register, Offset 0X034; Gptm Timer A Prescale (Gptmtapr) Register, Offset 0X038; Gptm Timer A Match (Gptmtamatchr) Register; Gptm Timer B Match (Gptmtbmatchr) Register - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 2-15. GPTM Timer A Match (GPTMTAMATCHR) Register Field Descriptions
Bit Field
31-0 TAMR 0x0000.

2.6.12 GPTM Timer B Match (GPTMTBMATCHR) Register, offset 0x034

The GPTM Timer B Match (GPTMTBMATCHR) register is loaded with a match value. Interrupts can be
generated when the timer value is equal to the value in this register in one-shot or periodic mode.
In Edge-Count mode, this register along with GPTMTBILR, determines how many edge events are
counted. The total number of edge events counted is equal to the value in GPTMTBILR minus this value.
In PWM mode, this value along with GPTMTBILR, determines the duty cycle of the output PWM signal.
When a GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are
loaded into the upper 16 bits of the GPTMTAMATCHR register. Reads from this register return the current
match value of Timer B and writes are ignored. In a 16-bit mode, bits 15:0 are used for the match value.
Bits 31:16 are reserved in both cases.
31
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 2-16. GPTM Timer B Match (GPTMTBMATCHR) Register Field Descriptions
Bit Field
31-16 Reserved
15-0 TBMR 0x0000.

2.6.13 GPTM Timer A Prescale (GPTMTAPR) Register, offset 0x038

The GPTM Timer A Prescale (GPTMTAPR) register allows software to extend the range of the 16-bit
timers in periodic and one-shot modes. In Edge-Count mode, this register is the MSB of the 24-bit count
value.
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
SPRUH22I – April 2012 – Revised November 2019
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Figure 2-16. GPTM Timer A Match (GPTMTAMATCHR) Register
Value Description
GPTM Timer A Match Register
FFFF
This value is compared to the GPTMTAR register to determine match events.
Figure 2-17. GPTM Timer B Match (GPTMTBMATCHR) Register
R-0
Value Description
Reserved
GPTM Timer B Match Register
FFFF
This value is compared to the GPTMTBR register to determine match events.
Figure 2-18. GPTM Timer A Prescale (GPTMTAPR) Register
Reserved
R-0
Copyright © 2012–2019, Texas Instruments Incorporated
TAMR
R/W-1
16 15
Register Descriptions
TBMR
R/W-1
8 7
TAPSR
R/W-0
M3 General-Purpose Timers
0
0
0
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