Ctomipcset Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

System Control Registers
Bit Field
31 IPC32
30 IPC31
29 IPC30
28 IPC29
27 IPC28
26 IPC27
25 IPC26
24 IPC25
23 IPC24
22 IPC23
21 IPC22
20 IPC21
19 IPC20
18 IPC19
17 IPC18
16 IPC17
15 IPC16
14 IPC15
13 IPC14
12 IPC13
282
System Control and Interrupts
Table 1-177. CTOMIPCSET Register Field Descriptions
Value Description
0 CTOMIPCSET Flag 32. C28 to M3 core IPC flag 32 set. If a bit is set by writing a '1' then the
corresponding bit in CTOMIPCFLG is set. The status of this bit is not readable in this register – it is
readable in the CTOMIPCFLG and STS registers.
0 CTOMIPCSET Flag 31. C28 to M3 core IPC flag 31 set. If a bit is set by writing a '1' then the
corresponding bit in CTOMIPCFLG is set. The status of this bit is not readable in this register – it is
readable in the CTOMIPCFLG and STS registers.
0 CTOMIPCSET Flag 30. C28 to M3 core IPC flag 30 set. If a bit is set by writing a '1' then the
corresponding bit in CTOMIPCFLG is set. The status of this bit is not readable in this register – it is
readable in the CTOMIPCFLG and STS registers
0 CTOMIPCSET Flag 29. C28 to M3 core IPC flag 29 set. If a bit is set by writing a '1' then the
corresponding bit in CTOMIPCFLG is set. The status of this bit is not readable in this register – it is
readable in the CTOMIPCFLG and STS registers.
0 CTOMIPCSET Flag 28. C28 to M3 core IPC flag 28 set. If a bit is set by writing a '1' then the
corresponding bit in CTOMIPCFLG is set. The status of this bit is not readable in this register – it is
readable in the CTOMIPCFLG and STS registers.
0 CTOMIPCSET Flag 27. C28 to M3 core IPC flag 27 set. If a bit is set by writing a '1' then the
corresponding bit in CTOMIPCFLG is set. The status of this bit is not readable in this register – it is
readable in the CTOMIPCFLG and STS registers.
0 CTOMIPCSET Flag 26. C28 to M3 core IPC flag 26 set. If a bit is set by writing a '1' then the
corresponding bit in CTOMIPCFLG is set. The status of this bit is not readable in this register – it is
readable in the CTOMIPCFLG and STS registers.
0 CTOMIPCSET Flag 25. C28 to M3 core IPC flag 25 set. If a bit is set by writing a '1' then the
corresponding bit in CTOMIPCFLG is set. The status of this bit is not readable in this register – it is
readable in the CTOMIPCFLG and STS registers.
0 CTOMIPCSET Flag 24. C28 to M3 core IPC flag 24 set. If a bit is set by writing a '1' then the
corresponding bit in CTOMIPCFLG is set. The status of this bit is not readable in this register – it is
readable in the CTOMIPCFLG and STS registers.
0 CTOMIPCSET Flag 23. C28 to M3 core IPC flag 23 set. If a bit is set by writing a '1' then the
corresponding bit in CTOMIPCFLG is set. The status of this bit is not readable in this register – it is
readable in the CTOMIPCFLG and STS registers.
0 CTOMIPCSET Flag 22. C28 to M3 core IPC flag 22 set. If a bit is set by writing a '1' then the
corresponding bit in CTOMIPCFLG is set. The status of this bit is not readable in this register – it is
readable in the CTOMIPCFLG and STS registers.
0 CTOMIPCSET Flag 21. C28 to M3 core IPC flag 21set. If a bit is set by writing a '1' then the
corresponding bit in CTOMIPCFLG is set. The status of this bit is not readable in this register – it is
readable in the CTOMIPCFLG and STS registers.
0 CTOMIPCSET Flag 20. C28 to M3 core IPC flag 20 set. If a bit is set by writing a '1' then the
corresponding bit in CTOMIPCFLG is set. The status of this bit is not readable in this register – it is
readable in the CTOMIPCFLG and STS registers.
0 CTOMIPCSET Flag 19. C28 to M3 core IPC flag 19 set. If a bit is set by writing a '1' then the
corresponding bit in CTOMIPCFLG is set. The status of this bit is not readable in this register – it is
readable in the CTOMIPCFLG and STS registers.
0 CTOMIPCSET Flag 18. C28 to M3 core IPC flag 18 set. If a bit is set by writing a '1' then the
corresponding bit in CTOMIPCFLG is set. The status of this bit is not readable in this register – it is
readable in the CTOMIPCFLG and STS registers.
0 CTOMIPCSET Flag 17. C28 to M3 core IPC flag 17 set. If a bit is set by writing a '1' then the
corresponding bit in CTOMIPCFLG is set. The status of this bit is not readable in this register – it is
readable in the CTOMIPCFLG and STS registers.
0 CTOMIPCSET Flag 16. C28 to M3 core IPC flag 16 set. If a bit is set by writing a '1' then the
corresponding bit in CTOMIPCFLG is set. The status of this bit is not readable in this register – it is
readable in the CTOMIPCFLG and STS registers.
0 CTOMIPCSET Flag 15. C28 to M3 core IPC flag 15 set. If a bit is set by writing a '1' then the
corresponding bit in CTOMIPCFLG is set. The status of this bit is not readable in this register – it is
readable in the CTOMIPCFLG and STS registers.
0 CTOMIPCSET Flag 14. C28 to M3 core IPC flag 14 set. If a bit is set by writing a '1' then the
corresponding bit in CTOMIPCFLG is set. The status of this bit is not readable in this register – it is
readable in the CTOMIPCFLG and STS registers.
0 CTOMIPCSET Flag 13. C28 to M3 core IPC flag 13 set. If a bit is set by writing a '1' then the
corresponding bit in CTOMIPCFLG is set. The status of this bit is not readable in this register – it is
readable in the CTOMIPCFLG and STS registers.
Copyright © 2012–2019, Texas Instruments Incorporated
SPRUH22I – April 2012 – Revised November 2019
Submit Documentation Feedback
www.ti.com