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Register Descriptions
Table 2-9. GPTM Interrupt Mask (GPTMIMR) Register Field Descriptions (continued)
Bit
Field
9
CBMIM
8
TBTOIM
7-5
Reserved
4
TAMIM
3
RTCIM
2
CAEIM
1
CAMIM
0
TATOIM
2.6.6 GPTM Raw Interrupt Status (GPTMRIS) Register, offset 0x01C
The GPTM Raw Interrupt Status (GPTMRIS) register shows the state of the GPTM's internal interrupt
signal. These bits are set whether or not the interrupt is masked in the GPTMIMR register. Each bit can be
cleared by writing a 1 to its corresponding bit in GPTMICR.
31
15
Reserved
7
6
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 2-10. GPTM Raw Interrupt Status (GPTMRIS) Register Field Descriptions
Bit
Field
31-12
11
TBMRIS
314
M3 General-Purpose Timers
Value
Description
GPTM Capture B Match Interrupt Mask
0
Interrupt is disabled.
1
Interrupt is enabled.
GPTM Timer B Time-Out Interrupt Mask
0
Interrupt is disabled.
1
Interrupt is enabled.
GPTM Timer A Mode Match Interrupt Mask
0
Interrupt is disabled.
1
Interrupt is enabled.
GPTM RTC Interrupt Mask
0
Interrupt is disabled.
1
Interrupt is enabled.
GPTM Capture A Event Interrupt Mask
0
Interrupt is disabled.
1
Interrupt is enabled.
GPTM Capture A Match Interrupt Mask
0
Interrupt is disabled.
1
Interrupt is enabled.
GPTM Timer A Time-Out Interrupt Mask
0
Interrupt is disabled.
1
Interrupt is enabled.
Figure 2-11. GPTM Raw Interrupt Status (GPTMRIS) Register
12
R-0
5
4
TAMRIS
R-0
Value
Description
Reserved
GPTM Timer B Mode Match Raw Interrupt
0
The match value has not been reached
1
The TBMIE bit is set in the GPTMTBMR register, and the match value in the GPTMTBMATCHR
register has been reached when in the one-shot and periodic modes.
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
11
10
TBMRIS
CBERIS
R-0
R-0
3
2
RTCRIS
CAERIS
R-0
R-0
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
16
9
8
CBMRIS
TBTORIS
R-0
R-0
1
0
CAMRIS
TATORIS
R-0
R-0
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