Epi Host-Bus 8 Configuration (Epihb8Cfg) Register, Offset 0X010; Epi Host-Bus 8 Configuration (Epihb8Cfg) Register [Offset 0X010]; Epi Host-Bus 8 Configuration (Epihb8Cfg) Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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17.11.5 EPI Host-Bus 8 Configuration (EPIHB8CFG) Register, offset 0x010

NOTE: The MODE field in the EPICFG register determines which configuration register is accessed

for offsets 0x010 and 0x014.

To access EPIHB8CFG, the MODE field must be 0x2.

The Host Bus 8 Configuration register is activated when the HB8 mode is selected. The HB8 mode

supports muxed address/data (overlay of lower 8 address and all 8 data pins), separate address/data, and

address-less FIFO mode. Note that this register is reset when the MODE field in the EPICFG register is

changed. If another mode is selected and the HB8 mode is selected again, the values must be

reinitialized.

This mode is intended to support SRAMs, Flash memory(read), FIFOs, CPLDs/FPGAs, and devices with

an MCU/Host Bus slave or 8-bit FIFO interface support.

If less address pins are required, the corresponding AFSEL bit (see the GPIO chapter) should not be

enabled so the EPI controller does not drive those pins, and they are available as standard GPIOs.

EPI Host-Bus 8 Mode can be configured to use one to four chip selects with and without the use of ALE. If

an alternative to chip selects are required, a chip enable can be handled in one of three ways:

1. Manually control via GPIOs.

2. Associate one or more upper address pins to CE. Because CE is normally CE, lower addresses are

not used. For example, if pins EPI0S27 and EPI0S26 are used for device 1 and 0 respectively, then

address 0x6800.0000 accesses device 0 (device 1 has its CE high), and 0x6400.0000 accesses

device 1 (device 0 has its CE high). The pull-up behavior on the corresponding GPIOs must be

properly configured to ensure that the pins are disabled when the interface is not in use.

3. With certain SRAMs, the ALE can be used as CEn because the address remains stable after the ALE

strobe. The subsequent WR or RD signals write or read when ALE is low thus providing CE

functionality.

Figure 17-32. EPI Host-Bus 8 Configuration (EPIHB8CFG) Register [offset 0x010]

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 17-18. EPI Host-Bus 8 Configuration (EPIHB8CFG) Register Field Descriptions

External Peripheral Interface (EPI)

The EPI clock is free running.

The EPI clock is held low.

SPRUH22I – April 2012 – Revised November 2019

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