Exception And Interrupts; M3Nmi Configuration (Mnmicfg) Register; M3Nmi Configuration (Mnmicfg) Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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System Control Registers

Table 1-68. C28 Wait-In-Reset (CWIR) Register Field Descriptions (continued)

1.13.5 Exception and Interrupts

NOTE: Clearing all latched NMI error flag conditions will stop the NMI watchdog counter and reset it.

Any new error condition that is latched will restart the counter.

The user should clear the NMI interrupt flag and clear all flags together to generate a new

interrupt if a new error event occurs.

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 1-69. M3NMI Configuration (MNMICFG) Register Field Descriptions

System Control and Interrupts

Latched State of EMU0 Pin

The state of EMU0 pin is latched on reset (XRS AND POR) or when the SAMPLE bit is triggered.

Reading this bit will give the state of the EMU0 pin on reset or when sampled.

Has no effect

Forces the bit to "1"

Figure 1-58. M3NMI Configuration (MNMICFG) Register

ACIBERR NMI Enable

This bit enables the ACIBERR NMI condition to generate an NMI interrupt to the M3 CPU. Once

enabled, the bit cannot be cleared by the user. Only a device reset causing M3 reset will clear the

bit. Writes of 0 are ignored. Reading the bit will indicate if the ACIBERR NMI is enabled or disabled.

Note: The ACIBERR NMI condition needs to be disabled at reset.

ACIBERR NMI disabled

ACIBERR NMI enabled

This bit is always set to '1', meaning any NMI condition will generate an NMI interrupt to the M3

CPU and kick off the NMI watchdog counter. The bit cannot be cleared by the user.

SPRUH22I – April 2012 – Revised November 2019

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