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System Control Registers
Table 1-170. M3 to C28 IPC Set (MTOCIPCSET) Field Descriptions (continued)
Bit
Field
2
IPC3
1
IPC2
0
IPC1
1.13.11.2 M3 to C28 IPC Clear (MTOCIPCCLR) Register
31
30
IPC32
IPC31
W-0
W-0
23
22
IPC24
IPC23
W-0
W-0
15
14
IPC16
IPC15
W-0
W-0
7
6
IPC8
IPC7
W-0
W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-171. M3 to C28 IPC Clear (MTOCIPCCLR) Register Field Descriptions
Bit
Field
31
IPC32
30
IPC31
29
IPC30
28
IPC29
27
IPC28
26
IPC27
25
IPC26
24
IPC25
272
System Control and Interrupts
Value
Description
0
MTOCIPCSET Interrupt 3. M3 to C28 IPC interrupt 3 request set. If this bit is set by writing a '1'
then MTOCINT1 is raised to the C28 PIE. The status of this bit is not readable in this register – it is
readable in the corresponding bit in the MTOCIPCFLG and STS registers.
0
MTOCIPCSET Interrupt 2. M3 to C28 IPC interrupt 2 request set. If this bit is set by writing a '1'
then MTOCINT1 is raised to the C28 PIE. The status of this bit is not readable in this register – it is
readable in the corresponding bit in the MTOCIPCFLG and STS registers.
0
MTOCIPCSET Interrupt 1. M3 to C28 IPC interrupt 1 request set. If this bit is set by writing a '1'
then MTOCINT1 is raised to the C28 PIE. The status of this bit is not readable in this register – it is
readable in the corresponding bit in the MTOCIPCFLG and STS registers.
Figure 1-159. M3 to C28 IPC Clear (MTOCIPCCLR) Register
29
28
IPC30
IPC29
W-0
W-0
21
20
IPC22
IPC21
W-0
W-0
13
12
IPC14
IPC13
W-0
W-0
5
4
IPC6
IPC5
W-0
W-0
Value
Description
0
MTOCIPCCLR Flag 32. M3 to C28 core IPC flag 32 clear. If a bit is cleared by writing a '1' then the
corresponding bit in MTOCIPCFLG is cleared. The status of this bit is not readable in this register –
it is readable in the MTOCIPCFLG and STS registers.
0
MTOCIPCCLR Flag 31. M3 to C28 core IPC flag 31 clear. If a bit is cleared by writing a '1' then the
corresponding bit in MTOCIPCFLG is cleared. The status of this bit is not readable in this register –
it is readable in the MTOCIPCFLG and STS registers.
0
MTOCIPCCLR Flag 30. M3 to C28 core IPC flag 30 clear. If a bit is cleared by writing a '1' then the
corresponding bit in MTOCIPCFLG is cleared. The status of this bit is not readable in this register –
it is readable in the MTOCIPCFLG and STS registers.
0
MTOCIPCCLR Flag 29. M3 to C28 core IPC flag 29 clear. If a bit is cleared by writing a '1' then the
corresponding bit in MTOCIPCFLG is cleared. The status of this bit is not readable in this register –
it is readable in the MTOCIPCFLG and STS registers.
0
MTOCIPCCLR Flag 28. M3 to C28 core IPC flag 28 clear. If a bit is cleared by writing a '1' then the
corresponding bit in MTOCIPCFLG is cleared. The status of this bit is not readable in this register –
it is readable in the MTOCIPCFLG and STS registers.
0
MTOCIPCCLR Flag 27. M3 to C28 core IPC flag 27 clear. If a bit is cleared by writing a '1' then the
corresponding bit in MTOCIPCFLG is cleared. The status of this bit is not readable in this register –
it is readable in the MTOCIPCFLG and STS registers.
0
MTOCIPCCLR Flag 26. M3 to C28 core IPC flag 26 clear. If a bit is cleared by writing a '1' then the
corresponding bit in MTOCIPCFLG is cleared. The status of this bit is not readable in this register –
it is readable in the MTOCIPCFLG and STS registers.
0
MTOCIPCCLR Flag 25. M3 to C28 core IPC flag 25 clear. If a bit is cleared by writing a '1' then the
corresponding bit in MTOCIPCFLG is cleared. The status of this bit is not readable in this register –
it is readable in the MTOCIPCFLG and STS registers.
Copyright © 2012–2019, Texas Instruments Incorporated
27
26
IPC28
IPC27
W-0
W-0
19
18
IPC20
IPC19
W-0
W-0
11
10
IPC12
IPC11
W-0
W-0
3
2
IPC4
IPC3
W-0
W-0
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
25
24
IPC26
IPC25
W-0
W-0
17
16
IPC18
IPC17
W-0
W-0
9
8
IPC10
IPC9
W-0
W-0
1
0
IPC2
IPC1
W-0
W-0
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