Event-Trigger Clear Register And Mirror Register (Etclr / Etclrm); Event-Trigger Force Register (Etfrc); Event-Trigger Clear Register And Mirror Register (Etclr / Etclrm) Field Descriptions; Event-Trigger Force Register (Etfrc) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Registers
Figure 7-137. Event-Trigger Clear Register and Mirror Register (ETCLR / ETCLRM)
15
7
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-89. Event-Trigger Clear Register and Mirror Register (ETCLR / ETCLRM) Field Descriptions
Bit Field
15-4 Reserved
3 SOCB
2 SOCA
1 Reserved
0 INT
15
7
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-90. Event-Trigger Force Register (ETFRC) Field Descriptions
Bit Field
15-4 Reserved
3 SOCB
2 SOCA
1 Reserved
0 INT
786
C28 Enhanced Pulse Width Modulator (ePWM) Module
4
R-0
Value Description
Reserved
ePWM ADC Start-of-Conversion B (EPWMxSOCB) Flag Clear Bit
0 Writing a 0 has no effect. Always reads back a 0
1 Clears the ETFLG[SOCB] flag bit
ePWM ADC Start-of-Conversion A (EPWMxSOCA) Flag Clear Bit
0 Writing a 0 has no effect. Always reads back a 0
1 Clears the ETFLG[SOCA] flag bit
Reserved
ePWM Interrupt (EPWMx_INT) Flag Clear Bit
0 Writing a 0 has no effect. Always reads back a 0
1 Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated
Figure 7-138. Event-Trigger Force Register (ETFRC)
4
R-0
Value Description
Reserved
SOCB Force Bit. The SOCB pulse will only be generated if the event is enabled in the ETSEL
register. The ETFLG[SOCB] flag bit will be set regardless.
0 Has no effect. Always reads back a 0.
1 Generates a pulse on EPWMxSOCB and sets the SOCBFLG bit. This bit is used for test purposes.
SOCA Force Bit. The SOCA pulse will only be generated if the event is enabled in the ETSEL
register. The ETFLG[SOCA] flag bit will be set regardless.
0 Writing 0 to this bit will be ignored. Always reads back a 0.
1 Generates a pulse on EPWMxSOCA and set the SOCAFLG bit. This bit is used for test purposes.
0 Reserved
INT Force Bit. The interrupt will only be generated if the event is enabled in the ETSEL register.
The INT flag bit will be set regardless.
0 Writing 0 to this bit will be ignored. Always reads back a 0.
1 Generates an interrupt on EPWMxINT and set the INT flag bit. This bit is used for test purposes.
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R = 0
3 2
SOCB SOCA
R/W-0 R/W-0
Reserved
R-0
3 2
SOCB SOCA
R/W-0 R/W-0
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
8
1 0
Reserved INT
R-0 R/W-0
8
1 0
Reserved INT
R-0 R/W-0
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