Texas Instruments MSPM0G 51 Series Manual

MSPM0Gx51x Mixed-Signal Microcontrollers With CAN-FD Interface

1 Features

• Core
– Arm ® 32-bit Cortex
protection unit, frequency up to 80MHz
• Functional Safety-Compliant
– Developed for functional safety applications
– Functional Safety Manual and FMEDA
available to aid in functional safety system
design
– Systematic capability up to ASIL B targeted
• Operating characteristics
– Extended temperature: –40°C up to 125°C
– Wide supply voltage range: 1.62V to 3.6V
• Memories
– Up to 512KB of flash memory with error
correction code (ECC)
• Dual-bank with address swap for OTA
updates
– 16KB data flash bank with ECC protection
– 128KB total SRAM
• SRAM (Bank 0): 64kB SRAM with ECC
protection or hardware parity, and retention
down to STANDBY mode
• SRAM (Bank 1) : 64kB SRAM with retention
down to SLEEP mode
• High-performance analog peripherals
– Two simultaneous sampling 12-bit 4Msps
analog-to-digital converters (ADCs) with up to
27 external channels
• 14-bit effective resolution at 250ksps with
hardware averaging
– One 12-bit 1-MSPS digital-to-analog converter
with integrated output buffer (DAC)
– Three high-speed comparators (COMP) with
integrated 8-bit reference DACs
• 32ns propagation delay in high-speed mode
• Support low-power mode operation down to
<1µA
– Programmable analog connections between
ADC, COMP and DAC
– Configurable 1.4V or 2.5V internal shared
voltage reference (VREF)
– Integrated temperature sensor
• Optimized low-power modes
– RUN: 121µA/MHz (CoreMark)
– SLEEP: 614µA at 4MHz
– STOP: 56µA at 32 kHz
– STANDBY: 1.7µA with RTC and SRAM
retention
– SHUTDOWN: 93nA with IO wake-up capability
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change
without notice.
® M0+ CPU with memory
targeted
• Intelligent digital peripherals
– 12-channel DMA controller
– Math accelerator supports DIV, SQRT, MAC
and TRIG computations
– Nine timers support up to 28 PWM channels
• Three 16-bit general-purpose timers
• Two 16-bit general-purpose timers support
QEI
• One 16-bit general-purpose timer support
low-power operation in STANDBY mode
• One 32-bit high-resolution general-purpose
timer
• Two 16-bit advanced timers with deadband
support and complimentary outputs up to 12
PWM channels
– Two windowed watchdog timers (WWDT), one
independent watchdog timer (IWDT)
– RTC with alarm and calendar mode
• Enhanced communication interfaces
– Seven UART interfaces
• Two supporting LIN, IrDA, DALI, Smart
Card, Manchester
• Five basic instances, including one
supporting low-power operation in
STANDBY mode
2
– Three I C interfaces supporting up to FM+
(1Mbit/s), SMBus/PMBus, and wakeup from
STOP mode
– Three SPIs supports up to 32Mbits/s
– Two Controller Area Network (CAN) interfaces
support CAN 2.0 A or B and CAN-FD
• Clock system
– Internal 4 to 32MHz oscillator with up to ±1.2%
accuracy (SYSOSC)
– Phase-locked loop (PLL) up to 80MHz
– Internal 32kHz low-frequency oscillator
(LFOSC) with ±3% accuracy
– External 4 to 48MHz crystal oscillator (HFXT)
– External 32kHz crystal oscillator(LFXT)
– External clock input
• Data integrity and encryption
– AES-128/256 accelerator with support for GCM/
GMAC, CCM/CBC-MAC, CBC, CTR
– Secure Key Storage for up to four AES keys
– Flexible firewalls for protecting code and data
– True random number generator (TRNG)
– Cyclic redundancy checker (CRC-16, CRC-32)
– Extensive security features
• Flexible I/O features
– Up to 94 GPIOs
• Two 5V-tolerant open-drain IOs
MSPM0G3519, MSPM0G3518
MSPM0G1519, MSPM0G1518
SLASFA2 – NOVEMBER 2024