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12.1 Enhanced SPI Module Overview
Figure 12-1
shows the SPI CPU interfaces.
SPISIMO
SPISOMI
GPIO
SPICLK
MUX
SPISTE
The SPI module features include:
•
SPISOMI: SPI slave-output/master-input pin
•
SPISIMO: SPI slave-input/master-output pin
•
SPISTE: SPI slave transmit-enable pin
•
SPICLK: SPI serial-clock pin
NOTE: All four pins can be used as GPIO, if the SPI module is not used.
•
Two operational modes: master and slave
•
Baud rate: 125 different programmable rates. The maximum baud rate that can be employed is limited
by the maximum speed of the I/O buffers used on the SPI pins. See the device-specific data sheet for
more details.
•
Data word length: one to sixteen data bits
•
•
Four clocking schemes (controlled by clock polarity and clock phase bits) include:
– Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the
rising edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
•
Simultaneous receive and transmit operation (transmit function can be disabled in software)
•
Transmitter and receiver operations are accomplished through either interrupt- driven or polled
algorithms.
SPRUH22I – April 2012 – Revised November 2019
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Figure 12-1. SPI CPU Interface
System
Low speed
control
prescaler
block
SPIAENCLK
LSPCLK
SPI
Copyright © 2012–2019, Texas Instruments Incorporated
Enhanced SPI Module Overview
SYSCLKOUT
CPU
SYSRS
SPIINT/RXINT
TXINT
C28 Serial Peripheral Interface (SPI)
PIE
block
945