Host-Bus Write Cycle With Multiplexed Address And Data And Ale With Dual Or Quad Cs; Continuous Read Mode Accesses; Write Followed By Read To External Fifo - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Table of Contents

Host Bus Mode

Figure 17-11. Host-Bus Write Cycle with Multiplexed Address and Data and ALE with Dual or Quad CS

CS0/CS1/CS2/CS3

EPI0S26 EPI0S27/

EPI0S34 EPI0S33)

BSEL0/ BSEL1

(high order , non-muxed)

Address/Data

BSEL0 and BSEL1 are available in Host-Bus16 mode only .

Figure 17-12

shows continuous read mode accesses. In this mode, reads are performed by keeping the

read mode selected (output enable is asserted) and then changing the address pins. The data pins are

changed by the SRAM after the address pins change.

FIFO mode accesses are the same as normal read and write accesses, except that the ALE signal and

address pins are not present. Two input signals can be used to indicate when the XFIFO is full or empty to

gate transactions and avoid overruns and underruns. The FFULL and FEMPTY signals are synchronized

and must be recognized as asserted by the microcontroller for two system clocks before they affect

transaction status. The MAXWAIT field in the EPIHBnCFG register defines the maximum number of EPI

clocks to wait while the FEMPTY or FFULL signal is holding off a transaction.

FEMPTY signal should respond to a write and read from the XFIFO.

FEMPTY and FFULL signals should respond to two writes and one read from an external FIFO that

contains two entries.

External Peripheral Interface (EPI)

Figure 17-12. Continuous Read Mode Accesses

Figure 17-13. Write Followed by Read to External FIFO

Figure 17-14

SPRUH22I – April 2012 – Revised November 2019

Figure 17-13

shows how the

Submit Documentation Feedback

Chapters

Table of Contents