Watchdog Raw Interrupt Status (Wdtris) Register, Offset 0X010; Watchdog Masked Interrupt Status (Wdtmis) Register, Offset 0X014; Watchdog Raw Interrupt Status (Wdtris) Register; Watchdog Masked Interrupt Status (Wdtmis) Register - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Register Descriptions

3.3.5 Watchdog Raw Interrupt Status (WDTRIS) Register, offset 0x010

The watchdog raw interrupt status (WDTRIS) register is the raw interrupt status register. Watchdog
interrupt events can be monitored via this register if the controller interrupt is masked.
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 3-6. Watchdog Raw Interrupt Status (WDTRIS) Register Field Descriptions
Bit Field
31-1 Reserved
0 WDTRIS

3.3.6 Watchdog Masked Interrupt Status (WDTMIS) Register, offset 0x014

The watchdog masked interrupt status (WDTMIS) register is the masked interrupt status register. The
value of this register is the logical AND of the raw interrupt bit and the watchdog interrupt enable bit.
Figure 3-7. Watchdog Masked Interrupt Status (WDTMIS) Register
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 3-7. Watchdog Masked Interrupt Status (WDTMIS) Register Field Descriptions
Bit Field
31-1 Reserved
0 WDTMIS
330
M3 Watchdog Timers
Figure 3-6. Watchdog Raw Interrupt Status (WDTRIS) Register
Reserved
R-0
Value Description
Reserved
Watchdog raw interrupt status
0 The watchdog has not timed out.
1 A watchdog time-out event has occurred.
Reserved
R-0
Value Description
Reserved
Watchdog masked interrupt status
0 The watchdog has not timed out or the watchdog timer interrupt is masked.
1 A watchdog time-out event has been signalled to the interrupt controller.
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SPRUH22I – April 2012 – Revised November 2019
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1 0
WDTRIS
R-0
1 0
WDTMIS
R-0