Usb External Power Control Register (Usbepc), Offset 0X400; Usb External Power Control Register (Usbepc); Usb External Power Control Register (Usbepc) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Register Descriptions

18.5.47 USB External Power Control Register (USBEPC), offset 0x400

The USB external power control 32-bit register (USBEPC) specifies the function of the two-pin external
power interface (USB0EPEN and USB0PFLT). The assertion of the power fault input may generate an
automatic action, as controlled by the hardware configuration registers. The automatic action is necessary
because the fault condition may require a response faster than one provided by firmware.
Mode(s): OTG A or Host
USBEPC is shown in
31
15
7 6
Reserved PFLTAEN
R-0 R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 18-63. USB External Power Control Register (USBEPC) Field Descriptions
Bit Field Value
31-10 Reserved 0
9-8 PFLTACT
0h
1h
2h
3h
7 Reserved 0
6 PFLTAEN
0
1
5 PFLTSEN
0
1
4 PFLTEN
0
1
3 Reserved 0
1360
M3 Universal Serial Bus (USB) Controller
OTG B or Device
Figure 18-58 and described in
Figure 18-58. USB External Power Control Register (USBEPC)
Reserved
R-0
5 4
PFLTSEN PFLTEN
R/W-0 R/W-0
Description
Reserved
Power Fault Action. This bit field specifies how the USB0EPEN signal is changed when detecting a
USB power fault.
Unchanged. USB0EPEN is controlled by the combination of the EPEN and EPENDE bits.
Tristate. USB0EPEN is undriven (tristate).
Low. USB0EPEN is driven Low.
High. USB0EPEN is driven High.
Reserved
Power Fault Action Enable. This bit specifies whether a USB power fault triggers any automatic
corrective action regarding the driven state of the USB0EPEN signal.
Disabled. USB0EPEN is controlled by the combination of the EPEN and EPENDE bits.
Enabled. The USB0EPEN output is automatically changed to the state specified by the PFLTACT field.
Power Fault Sense. This bit specifies the logical sense of the USB0PFLT input signal that indicates an
error condition.
The complementary state is the inactive state.
Low Fault. If USB0PFLT is driven Low, the power fault is signaled internally (if enabled by the PFLTEN
bit).
High Fault. If USB0PFLT is driven High, the power fault is signaled internally (if enabled by the PFLTEN
bit).
Power Fault Input Enable. This bit specifies whether the USB0PFLT input signal is used in internal
logic.
Not Used. The USB0PFLT signal is ignored.
Used. The USB0PFLT signal is used internally
Reserved
Copyright © 2012–2019, Texas Instruments Incorporated
Table 18-63.
Reserved
R-0
10
3 2
Reserved EPENDE
R-0 R/W-0
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
16
9 8
PFLTACT
R/W-0
1 0
EPEN
R/W-0
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