Register Descriptions (I2C Slave); I2C Slave Own Address (I2Csoar), Offset 0X800; I2C Slave Control/Status (I2Cscsr), Offset 0X804; I2C Slave Own Address (I2Csoar) Register - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Register Descriptions (I2C Slave)

22.7 Register Descriptions (I2C Slave)
The remainder of this section lists and describes the I2C slave registers, in numerical order by address
offset.

22.7.1 I2C Slave Own Address (I2CSOAR), offset 0x800

The I2C Slave Own Address (I2CSOAR) register consists of seven address bits that identify the I2C
device on the I2C bus.
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-14. I2C Slave Own Address (I2CSOAR) Register Field Descriptions
Bit Field
31-5
6-0

22.7.2 I2C Slave Control/Status (I2CSCSR), offset 0x804

The I2C Slave Control/Status (I2CSCSR) register functions as a control register when written, and a
status register when read.
The first register and description in this section is Read-Only. The second register and description in this
section is Write-Only. This register is Read-Only.
Figure 22-25. I2C Slave Control/Status (I2CSCSR) Register (Read-Only)
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-15. I2C Slave Control/Status (I2CSCSR) Register Field Descriptions (Read-Only)
Bit Field
31-3 Reserved
2 FBR
1 TREQ
0 RREQ
1508
M3 Inter-Integrated Circuit (I2C) Interface
Figure 22-24. I2C Slave Own Address (I2CSOAR) Register
Reserved
R-0
Value Description
Reserved
00h I2C Slave Own Address
This field specifies bits A6 through A0 of the slave address.
Reserved
R-0
Value Description
Reserved
First Byte Received
0 The first byte has not been received.
1 The first byte following the slave's own address has been received.
This bit is only valid when the RREQ bit is set and is automatically cleared when data has been
read from the I2CSDR register.
Note: This bit is not used for slave transmit operations
Transmit Request
0 No outstanding transmit request.
1 The I2C controller has been addressed as a slave transmitter and is using clock stretching to delay
the master until data has been written to the I2CSDR register
Receive Request
0 No outstanding receive data
1 The I2C controller has outstanding receive data from the I2C master and is using clock stretching to
delay the master until the data has been read from the I2CSDR register
Copyright © 2012–2019, Texas Instruments Incorporated
7 6
3 2
FBR
R-0
SPRUH22I – April 2012 – Revised November 2019
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0
OAR
R/W-0
1 0
TREQ RREQ
R-0 R-0