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Exceptions and Interrupts Control
First, whenever a READ or WRITE strobe is generated, the READY signal is sampled on the very first
cycle. The READY signal should be low. If it is not low, then the ACIBERR NMI is triggered to both the
master and control subsystems irrespective of which subsystem issued the current READ or WRITE.
Second, if a read or write access is generated and the active cycle is not completed by a specified
timeout, then this indicates either READY was not generated or that READY is stuck high. The timeout
starts whenever a READ or WRITE access is activated across the ACIB. This time-out check is internally
implemented in ACIB hardware.
The INTS strobe signal is pulsed high for only one cycle. If this is not the case, this is an error and a pulse
is generated on ACIBERRNMI that is fed to both the master and control subsystems' NMI modules.
Apart from READ/WRITE and interrupts that pass through the ACIB, there are some trigger signals that
could get stuck high. In this case, triggers will get continually exported on the ACIB. If this happens, ACIB
accesses will get stalled which will then eventually cause the READY time-out to occur. Hence, the
READY timeout mechanism will capture this case.
The status of the READY and INTS signals' state can be read by both the master subsystem and control
subsystem by reading the MCIBSTATUS and CCIBSTATUS read-only registers.
An NMI is generated to both the master subsystem and control subsystem on this error condition.
1.5.3.2
Master Subsystem NMIWD Module
As explained previously, the master subsystem is equipped with an NMI Watchdog module whose function
is to make sure that a triggered non-maskable interrupt is handled by user software. This can be achieved
by clearing the error conditions and clearing the respective flags in the MNMIFLG register or by
acknowledging the NMI and gracefully shutting down the system. If none of the actions mentioned are
taken, then the MNMIWD counter keeps counting until the counter value reaches the MNMIWD period
register value. An MNMIWD reset will then be generated, which will reset the entire device. Please refer to
Section 1.3.1.5
for more details on the reset.
As shown in
Figure 1-3
register, which will trigger an NMI to the CPU and start the NMIWD counter. The NMIWD counter will keep
counting as long as the NMIINT bit of the MNMIFLG register is not cleared or a reset is generated.
The MNMIWD counter is clocked by the M3 system clock. The MNMIWDPRD register, which is the MNMI
Watchdog Period register, can be programmed with a period limit as per user requirements which sets the
clock cycle limit required for software to handle or acknowledge the NMI. A timeout condition that generate
the NMI watchdog reset means that the counter value of the MNMIWDCNT register reached the value
programmed in the period register, MNMIWDPRD.
1.5.3.2.1 Emulation Considerations
When the Cortex-M3 CPU is suspended (in debug halt), the NMI watchdog counter will be suspended.
1.5.3.3
Handling of MNMI
User software must clear all the flag bits which are set in the MNMIFLG register before clearing NMIINT,
bit 0 of the MNMIFLG register. If the user clears the NMIINT bit in the MNMIFLG register before clearing
all the individual flag bits, as soon as the NMIINT bit is cleared it will be set back to "1" again. This will
generate another back-to-back NMI to the master subsytem's CPU, and the NMIWD counter will start
counting again.
1.5.4 Control Subsystem PIE
The control subsystem supports the peripheral interrupt expansion block to handle different exceptions
and interrupts that occur on control subsystem modules during the device operation. The PIE enables
multiplexing of numerous interrupt sources into a smaller set of interrupt inputs. The PIE block can support
96 individual interrupts that are grouped into blocks of eight. Each group is fed into one of 12 core
interrupt lines (INT1 to INT12). Each of the 96 interrupts is supported by its own vector stored in a
100
System Control and Interrupts
above, any enabled NMI source can set the NMIINT respective bit in MNMIFLG
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SPRUH22I – April 2012 – Revised November 2019
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