Trip-Zone Clear Register And Mirror Register (Tzclr / Tzclrm); Trip-Zone Clear Register And Mirror Register (Tzclr / Tzclrm) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Registers
Figure 7-114. Trip-Zone Clear Register and Mirror Register (TZCLR / TZCLRM)
15 14
CBCPULSE
R/W-0
7 6
Reserved DCBEVT2
R-0 R/W1C-0
LEGEND: R/W = Read/Write; nC - write n to clear; R = Read only; -n = value after reset
Table 7-64. Trip-Zone Clear Register and Mirror Register (TZCLR / TZCLRM) Field Descriptions
Bit Field
15-14 CBCPULSE
13-7 Reserved
6 DCBEVT2
5 DCBEVT1
4 DCAEVT2
3 DCAEVT1
2 OST
1 CBC
0 INT
764
C28 Enhanced Pulse Width Modulator (ePWM) Module
13
5 4
DCBEVT1 DCAEVT2
R/W1C-0 R/W1C-0
Value Description
Clear Pulse for Cycle-By-Cycle (CBC) Trip Latch
This bit field determines which pulse clears the CBC trip latch.
00 CTR = zero pulse clears CBC trip latch. (Same as legacy designs.)
01 CTR = PRD pulse clears CBC trip latch.
10 CTR = zero or CTR = PRD pulse clears CBC trip latch.
11 CBC trip latch is not cleared
Reserved
Clear Flag for Digital Compare Output B Event 2
0 Writing 0 has no effect. This bit always reads back 0.
1 Writing 1 clears the DCBEVT2 event trip condition.
Clear Flag for Digital Compare Output B Event 1
0 Writing 0 has no effect. This bit always reads back 0.
1 Writing 1 clears the DCBEVT1 event trip condition.
Clear Flag for Digital Compare Output A Event 2
0 Writing 0 has no effect. This bit always reads back 0.
1 Writing 1 clears the DCAEVT2 event trip condition.
Clear Flag for Digital Compare Output A Event 1
0 Writing 0 has no effect. This bit always reads back 0.
1 Writing 1 clears the DCAEVT1 event trip condition.
Clear Flag for One-Shot Trip (OST) Latch
0 Has no effect. Always reads back a 0.
1 Clears this Trip (set) condition.
Clear Flag for Cycle-By-Cycle (CBC) Trip Latch
0 Has no effect. Always reads back a 0.
1 Clears this Trip (set) condition.
Global Interrupt Clear Flag
0 Has no effect. Always reads back a 0.
1 Clears the trip-interrupt flag for this ePWM module (TZFLG[INT]).
NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the
TZFLG[INT] bit is cleared and any of the other flag bits are set, then another interrupt pulse will be
generated. Clearing all flag bits will prevent further interrupts.
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
3 2
DCAEVT1 OST
R/W1C-0 R/W-0
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
8
1 0
CBC INT
R/W-0 R/W-0
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