Register Descriptions; Uart Data Register (Uartdr), Offset 0X000; Register Map - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Offset
0x000 UARTDR
0x004 UARTRSR/UARTEC
R
0x018 UARTFR
0x020 UARTILPR
0x024 UARTIBRD
0x028 UARTFBRD
0x02C UARTLCRH
0x030 UARTCTL
0x034 UARTIFLS
0x038 UARTIM
0x03C UARTRIS
0x040 UARTMIS
0x044 UARTICR
0x048 UARTDMACTL
0x090 UARTLCTL
0x094 UARTLSS
0x098 UARTLTIM
0xFD0 UARTPeriphID4
0xFD4 UARTPeriphID5
0xFD8 UARTPeriphID6
0xFDC UARTPeriphID7
0xFE0 UARTPeriphID0
0xFE4 UARTPeriphID1
0xFE8 UARTPeriphID2
0xFEC UARTPeriphID3
0xFF0 UARTPCellID0
0xFF4 UARTPCellID1
0xFF8 UARTPCellID2
0xFFC UARTPCellID3

21.7 Register Descriptions

The remainder of this section lists and describes the UART registers, in numerical order by address offset.

21.7.1 UART Data Register (UARTDR), offset 0x000

UARTDR is the data register (the interface to the FIFOs).
NOTE: This register is read-sensitive.
For transmitted data, if the FIFO is enabled, data written to this location is pushed onto the transmit FIFO.
If the FIFO is disabled, data is stored in the transmitter holding register (the bottom word of the transmit
FIFO). A write to this register initiates a transmission from the UART.
For received data, if the FIFO is enabled, the data byte and the 4-bit status (break, frame, parity, and
overrun) is pushed onto the 12-bit wide receive FIFO. If the FIFO is disabled, the data byte and status are
stored in the receiving holding register (the bottom word of the receive FIFO). The received data can be
retrieved by reading this register.
SPRUH22I – April 2012 – Revised November 2019
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Table 21-1. Register Map
Name Type
R/W
R/W
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
W1C
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Copyright © 2012–2019, Texas Instruments Incorporated
Reset
0x0000.0000 UART Data
0x0000.0000 UART Receive Status/Error Clear
0x0000.0090 UART Flag
0x0000.0000 UART IrDA Low-Power Register
0x0000.0000 UART Integer Baud-Rate Divisor
0x0000.0000 UART Fractional Baud-Rate Divisor
0x0000.0000 UART Line Control
0x0000.0300 UART Control
0x0000.0012 UART Interrupt FIFO Level Select
0x0000.0000 UART Interrupt Mask
0x0000.000F UART Raw Interrupt Status
0x0000.0000 UART Masked Interrupt Status
0x0000.0000 UART Interrupt Clear
0x0000.0000 UART DMA Control
0x0000.0000 UART LIN Control
0x0000.0000 UART LIN Snap Shot
0x0000.0000 UART LIN Timer
0x0000.0000 UART Peripheral Identification 4
0x0000.0000 UART Peripheral Identification 5
0x0000.0000 UART Peripheral Identification 6
0x0000.0000 UART Peripheral Identification 7
0x0000.0060 UART Peripheral Identification 0
0x0000.0000 UART Peripheral Identification 1
0x0000.0018 UART Peripheral Identification 2
0x0000.0001 UART Peripheral Identification 3
0x0000.000D UART PrimeCell Identification 0
0x0000.00F0 UART PrimeCell Identification 1
0x0000.0005 UART PrimeCell Identification 2
0x0000.00B1 UART PrimeCell Identification 3
M3 Universal Asynchronous Receivers/Transmitters (UARTs)
Register Descriptions
Description
1461