Set The Receive Sign-Extension And Justification Mode; 2-Bit Data Delay Used To Skip A Framing Bit; Register Bits Used To Set The Receive Sign-Extension And Justification Mode; Example: Use Of Rjust Field With 12-Bit Data Value Abch - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Table of Contents

15.8.13 Set the Receive Sign-Extension and Justification Mode

The RJUST bits (see

how it is justified.

Table 15-32. Register Bits Used to Set the Receive Sign-Extension and Justification Mode

15.8.13.1 Sign-Extension and the Justification

RJUST in SPCR1 selects whether data in RBR[1,2] is right- or left-justified (with respect to the MSB) in

DRR[1,2] and whether unused bits in DRR[1,2] are filled with zeros or with sign bits.

on an example 12-bit receive-data value ABCh. The second table shows the effect on an example 20-bit

receive-data value ABCDEh.

Table 15-33. Example: Use of RJUST Field With 12-Bit Data Value ABCh

Justification

Table 15-34. Example: Use of RJUST Field With 20-Bit Data Value ABCDEh

Justification

SPRUH22I – April 2012 – Revised November 2019

Submit Documentation Feedback

Figure 15-47. 2-Bit Data Delay Used to Skip a Framing Bit

15-32) determine whether data received by the McBSP is sign-extended and

Receive sign-extension and justification mode

Right justify data and zero fill MSBs in DRR[1,2]

Right justify data and sign extend it into the MSBs in

Left justify data and zero fill LSBs in DRR[1,2]

show the effects of various RJUST values. The first table shows the effect

Zero fill MSBs

Sign extend data into MSBs

Zero fill LSBs

Zero fill MSBs

Sign extend data into MSBs

Zero fill LSBs

C28 Multichannel Buffered Serial Port (McBSP)

Receiver Configuration

Table of Contents