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Table 1-105. System Clock Divider (SYSDIVSEL) Register Field Descriptions
Bit
Field
31-2
Reserved
1-0
SYSDIVSEL
1.13.7.3 System PLL Lock Status (SYSPLLSTS) Register
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-106. System PLL Lock Status (SYSPLLSTS) Register Field Descriptions
Bit
Field
31-2
Reserved
1
SPLLSLIPS
0
SYSPLLLOCKS
1.13.7.4 Master Subsystem Clock Divider (M3SSDIVSEL) Register
Figure 1-96. Master Subsystem Clock Divider (M3SSDIVSEL) Register
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
SPRUH22I – April 2012 – Revised November 2019
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Value
Description
Reserved
System Clock Divide Select
This bit selects between /8, /4, /2 and /1 for PLLSYSCLK (CLKIN to the C28 CPU as well as input
clock to the M3 subsystem and CIB clock pre-scalers). This clock is referred to as the C28 SS
clock. The configuration of the SYSDIVSEL bits is as follows.
00
Select C28 CLKIN Divide By 1 of PLLSYSCLK
01
Select C28 CLKIN Divide By 2 of PLLSYSCLK
10
Select C28 CLKIN Divide By 4 of PLLSYSCLK
11
Select C28 CLKIN Divide By 8 (at reset) of PLLSYSCLK
Figure 1-95. System PLL Lock Status (SYSPLLSTS) Register
Reserved
R-0:0
Value
Description
Reserved
System PLL Out-of-Range Status
This bit indicates whether the PLL is out of lock range.
Note: If a PLL out-of-lock condition is detected then an interrupt is generated to the NVIC; software
can decide to relock the PLL or switch to PLL bypass mode in the interrupt handler.
0
System PLL is not out of lock
1
System PLL is out of lock
System PLL Lock Status
This bit indicates whether the PLL is locked or not.
0
System PLL is not locked
1
System PLL is locked
Reserved
R-0:0
Copyright © 2012–2019, Texas Instruments Incorporated
System Control Registers
2
1
0
SPLLSLIP
SYSPLLLO
S
CKS
R-0
R-0
2
1
M3SSDIVSEL
R/W-10
System Control and Interrupts
0
223
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