Peripheral Interrupt Trigger Source Options - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Peripheral
CPU
ADC
External Interrupts
CPU Timers
McBSP
ePWM1
ePWM2
ePWM3
ePWM4
ePWM5
ePWM6
ePWM7
ePWM8
ePWM9
11.2.3 DMA Bus
The DMA bus architecture consists of a 22-bit address bus, a 32-bit data read bus, and a 32-bit data write
bus. Memories and register locations connected to the DMA bus are via interfaces that sometimes share
resources with the CPU memory or peripheral bus. Arbitration rules are defined in
following resources are connected to the DMA bus:
• L2/L3 C28x local RAM
• CTOM MSG RAM
• MTOC MSG RAM
• S0-S7 shared RAM
• ADC 1 memory-mapped result registers
• ADC 2 memory-mapped result registers
• McBSP data receive registers (DRR2/DRR1) and data transmit registers (DXR2/DXR1)
• ePWM1-9/HRPWM1-8 registers
SPRUH22I – April 2012 – Revised November 2019
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Table 11-1. Peripheral Interrupt Trigger Source Options
Interrupt Trigger Source
DMA Software bit (CHx.CONTROL.PERINTFRC) only
ADCINT 1
ADCINT 2
ADCINT3
ADCINT4
External Interrupt 1
External Interrupt 2
External Interrupt 3
Timer 0 Overflow
Timer 1 Overflow
Timer 2 Overflow
McBSP Transmit Buffer Empty
McBSP Receive Buffer Full
ADC Start of Conversion A
ADC Start of Conversion B
ADC Start of Conversion A
ADC Start of Conversion B
ADC Start of Conversion A
ADC Start of Conversion B
ADC Start of Conversion A
ADC Start of Conversion B
ADC Start of Conversion A
ADC Start of Conversion B
ADC Start of Conversion A
ADC Start of Conversion B
ADC Start of Conversion A
ADC Start of Conversion B
ADC Start of Conversion A
ADC Start of Conversion B
ADC Start of Conversion A
ADC Start of Conversion B
Copyright © 2012–2019, Texas Instruments Incorporated
Section 11.4. The
C28 Direct Memory Access (DMA) Module
Architecture
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