Exception Model; Exception States; Exception Types - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Exception Model

threads.
For more information about the synchronization primitive instructions, see the Cortex-M3 Instruction Set
Technical User's Manual.
24.7 Exception Model
The ARM Cortex-M3 processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle
all exceptions in Handler Mode. The processor state is automatically stored to the stack on an exception
and automatically restored from the stack at the end of the Interrupt Service Routine (ISR). The vector is
fetched in parallel to the state saving, enabling efficient interrupt entry. The processor supports tail-
chaining, which enables back-to-back interrupts to be performed without the overhead of state saving and
restoration.
Table 24-16 lists all exception types. Software can set eight priority levels on seven of these exceptions
(system handlers) as well as on 55 interrupts (listed in
Priorities on the system handlers are set with the NVIC System Handler Priority n (SYSPRIn) registers.
Interrupts are enabled through the NVIC Interrupt Set Enable n (ENn) register and prioritized with the
NVIC Interrupt Priority n (PRIn) registers. Priorities can be grouped by splitting priority levels into
preemption priorities and subpriorities. All the interrupt registers are described in Nested Vectored
Interrupt Controller (NVIC) in the Cortex-M3 Peripherals chapter.
Internally, the highest user-programmable priority (0) is treated as fourth priority, after a Reset, Non-
Maskable Interrupt (NMI), and a Hard Fault, in that order. Note that 0 is the default priority for all the
programmable priorities.
NOTE: After a write to clear an interrupt source, it may take several processor cycles for the NVIC to
see the interrupt source de-assert. Thus if the interrupt clear is done as the last action in an
interrupt handler, it is possible for the interrupt handler to complete while the NVIC sees the
interrupt as still asserted, causing the interrupt handler to be re-entered errantly. This
situation can be avoided by either clearing the interrupt source at the beginning of the
interrupt handler or by performing a read or write after the write to clear the interrupt source
(and flush the write buffer).
See Nested Vectored Interrupt Controller (NVIC) in the Cortex-M3 Peripherals chapter for more
information on exceptions and interrupts.

24.7.1 Exception States

Each exception is in one of the following states:
• Inactive.The exception is not active and not pending.
• Pending.The exception is waiting to be serviced by the processor. An interrupt request from a
peripheral or from software can change the state of the corresponding interrupt to pending.
• Active.An exception that is being serviced by the processor but has not completed.NoteAn exception
handler can interrupt the execution of another exception handler. In this case, both exceptions are in
the active state.
• Active and Pending.The exception is being serviced by the processor, and there is a pending
exception from the same source.

24.7.2 Exception Types

The exception types are:
• Reset. Reset is invoked on power up or a warm reset. The exception model treats reset as a special
form of exception. When reset is asserted, the operation of the processor stops, potentially at any point
in an instruction. When reset is deasserted, execution restarts from the address provided by the reset
entry in the vector table. Execution restarts as privileged execution in Thread mode.
• NMI. A non-maskable Interrupt (NMI) can be signaled using the NMI signal or triggered by software
using the Interrupt Control and State (INTCTRL) register. This exception has the highest priority other
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Cortex-M3 Processor
Table
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24-17).
SPRUH22I – April 2012 – Revised November 2019
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