Overview; System-Level Interface; System Component Details; Cortex-M3 Processor Block Diagram - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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24.3 Overview

The Cortex-M3 processor provides multiple interfaces using AMBA

low-latency memory accesses. The core supports unaligned data accesses and implements atomic bit

manipulation that enables faster peripheral controls, system spinlocks, and thread-safe Boolean data

The processor has a memory protection unit (MPU) that provides fine-grain memory control, enabling

applications to implement security privilege levels and separate code, data and stack on a task-by-task

The Cortex™-M3 processor includes the following system components:

A 24-bit count-down timer that can be used as a Real-Time Operating System (RTOS) tick timer or as

a simple counter (see System Timer (SysTick) in the Cortex-M3 Peripherals chapter).

Nested Vectored Interrupt Controller (NVIC)

An embedded interrupt controller that supports low latency interrupt processing (see Nested Vectored

Interrupt Controller (NVIC) in the Cortex-M3 Peripherals chapter).

System Control Block (SCB)

The programming model interface to the processor. The SCB provides system implementation

information and system control, including configuration, control, and reporting of system exceptions(

see System Control Block (SCB) in the Cortex-M3 Peripherals chapter).

Memory Protection Unit (MPU)

Improves system reliability by defining the memory attributes for different memory regions. The MPU

SPRUH22I – April 2012 – Revised November 2019

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Figure 24-1. Cortex-M3 Processor Block Diagram

Instructions

Private Peripheral

Adv. Peripheral

technology to provide high-speed,

Cortex-M3 Processor

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