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General-Purpose Input/Output (GPIO)
4.1.6.17 GPIO Port Control (GPIOPCTL) Register, offset 0x52C
The GPIOPCTL register is used in conjunction with the GPIOAFSEL register and selects the specific
peripheral signal for each GPIO pin when using the alternate function mode. Most bits in the GPIOAFSEL
register are cleared on reset, therefore GPIO pins are configured as GPIOs by default. When a bit is set in
the GPIOAFSEL register, the corresponding GPIO signal is controlled by an associated peripheral. The
GPIOPCTL register selects one out of a set of peripheral functions for each GPIO, providing additional
flexibility in signal definition.
Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0,
GPIODEN=0, GPIOPUR=0, and GPIOPCTL=0. A Power-On-Reset (POR) or asserting XRS puts the pins
back to their default state.
31
28
PMC7
R/W
15
12
PMC3
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-22. GPIO Port Control (GPIOPCTL) Register Field Descriptions
Bit
Field
31-28
PMC7
27-24
PMC6
23-20
PMC5
19-16
PMC4
15-12
PMC3
11-8
PMC2
7-4
PMC1
3-0
PMC0
358
General-Purpose Input/Output (GPIO)
Figure 4-20. GPIO Port Control (GPIOPCTL) Register
27
PMC6
R/W
11
PMC2
R/W
Value
Description
Port Mux Control 7
This field controls the configuration for GPIO pin 7.
Port Mux Control 6
This field controls the configuration for GPIO pin 6.
Port Mux Control 5
This field controls the configuration for GPIO pin 5.
Port Mux Control 4
This field controls the configuration for GPIO pin 4.
Port Mux Control 3
This field controls the configuration for GPIO pin 3.
Port Mux Control 2
This field controls the configuration for GPIO pin 2.
Port Mux Control 1
This field controls the configuration for GPIO pin 1.
Port Mux Control 0
This field controls the configuration for GPIO pin 0.
Copyright © 2012–2019, Texas Instruments Incorporated
24
23
PMC5
R/W
8
7
PMC1
R/W
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
20
19
PMC4
R/W
4
3
PMC0
R/W
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