Sci Control Register 1 (Scictl1); Sci Control Register 1 (Scictl1) - Address 7051H; Sci Control Register 1 (Scictl1) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

SCI Registers

13.3.3 SCI Control Register 1 (SCICTL1)

SCICTL1 controls the receiver/transmitter enable, TXWAKE and SLEEP functions, and the SCI software
reset.
7 6
Reserved RX ERR INT
ENA
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field Valu
e
7 Reserved
6 RX ERR INT
ENA
0
1
5 SW RESET
0
1
4 Reserved
3 TXWAKE
0
1
996
C28 Serial Communications Interface (SCI)
Figure 13-13. SCI Control Register 1 (SCICTL1) — Address 7051h
5 4
SW RESET Reserved
R/W-0 R-0
Table 13-10. SCI Control Register 1 (SCICTL1) Field Descriptions
Description
Reads return zero; writes have no effect.
SCI receive error interrupt enable. Setting this bit enables an interrupt if the RX ERROR bit (SCIRXST, bit 7)
becomes set because of errors occurring.
Receive error interrupt disabled
Receive error interrupt enabled
SCI software reset (active low). Writing a 0 to this bit initializes the SCI state machines and operating flags
(registers SCICTL2 and SCIRXST) to the reset condition.
The SW RESET bit does not affect any of the configuration bits.
All affected logic is held in the specified reset state until a 1 is written to SW RESET (the bit values following
a reset are shown beneath each register diagram in this section). Thus, after a system reset, re-enable the
SCI by writing a 1 to this bit.
Clear this bit after a receiver break detect (BRKDT flag, bit SCIRXST, bit 5).
SW RESET affects the operating flags of the SCI, but it neither affects the configuration bits nor restores the
reset values. Once SW RESET is asserted, the flags are frozen until the bit is deasserted.
The affected flags are as follows:
Value After SW SCI Flag
RESET
1
1 TX EMPTY
0 RXWAKE
0
0
0
0
0 RXRDY
0 RX ERROR
Writing a 0 to this bit initializes the SCI state machines and operating flags (registers SCICTL2 and
SCIRXST) to the reset condition.
After a system reset, re-enable the SCI by writing a 1 to this bit.
Reads return zero; writes have no effect.
SCI transmitter wake-up method select. The TXWAKE bit controls selection of the data-transmit feature,
depending on which transmit mode (idle-line or address-bit) is specified at the ADDR/IDLE MODE bit
(SCICCR, bit 3)
Transmit feature is not selected. In idle-line mode: write a 1 to TXWAKE, then write data to register
SCITXBUF to generate an idle period of 11 data bits In address-bit mode: write a 1 to TXWAKE, then write
data to SCITXBUF to set the address bit for that frame to 1
Transmit feature selected is dependent on the mode, idle-line or address-bit:
TXWAKE is not cleared by the SW RESET bit (SCICTL1, bit 5); it is cleared by a system reset or the
transfer of TXWAKE to the WUT flag.
Copyright © 2012–2019, Texas Instruments Incorporated
3
TXWAKE SLEEP
R/S-0
Register Bit
TXRDY SCICTL2, bit 7
SCICTL2, bit 6
SCIRXST, bit 1
PE SCIRXST, bit 2
OE SCIRXST, bit 3
FE SCIRXST, bit 4
BRKDT SCIRXST, bit 5
SCIRXST, bit 6
SCIRXST, bit 7
SPRUH22I – April 2012 – Revised November 2019
2 1
TXENA
R/W-0 R/W-0
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0
RXENA
R/W-0