Test Register (Can Test); Test Register (Can Test) [Offset = 0X14]; Test Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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CAN Control Registers

23.15.6 Test Register (CAN TEST)

The Test register (CAN TEST) is shown and described in the figure and table below.

LEGEND: R = Read; WP = Write Protected by Test bit; -n = value after reset; -U = Undefined

M3 Controller Area Network (CAN)

Table 23-9. Descriptions (continued)

Interrupt Identifier 0. This bit field indicates the source of the interrupt.

No interrupt is pending

Number of the mailbox which caused the interrupt.

Error and Status register value is not 0x07.

If several interrupts are pending, the CAN Interrupt register will point to the pending interrupt

with the highest priority. The CAN0INT interrupt line remains active until INT0ID reaches value

0 (the cause of the interrupt is reset) or until IE0 is cleared. The status interrupt has the

highest priority.

A message interrupt is cleared by clearing the mailbox's IntPnd bit.

Among the message interrupts, the mailbox's interrupt priority decreases with increasing

message number.

Figure 23-24. Test Register (CAN TEST) [offset = 0x14]

Table 23-10. Test Register Field Descriptions

External Loopback Mode

Receive Pin. Monitors the actual value of the CAN_RX pin

The CAN bus is dominant

The CAN bus is recessive

Control of CAN_TX pin Normal operation

CAN_TX is controlled by the CAN Core.

Sample Point can be monitored at CAN_TX pin.

CAN_TX pin drives a dominant value.

CAN_TX pin drives a recessive value.

Loopback Mode

SPRUH22I – April 2012 – Revised November 2019

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