Master Subsystem Clocks And Low Power Mode Configuration - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Clock Control
Figure 1-11. Master Subsystem Clocks and Low Power Mode Configuration
REGISTER
ACCESS
M3SSCLK
PERIPH
LOGIC
M3SSCLK
WDOG 0
RCC REG
uCRC
ACG (Auto Clock Gate)
NMI WDOG
PERIPHERAL
M3CLKENBx
CLOCK
ENABLES
GP TIMER (4)
SSI (4)
RCGC REG
SCGS REG
DCGC REG
UART (5)
DC REG
( GLOBAL PERIPHERAL ENABLES )
2
I C (2)
EMAC
EPI
uDMA
32KHZCLK
X2
X1
INTERNAL
OSC
CLOCKFAIL
M3 NMI
10MHZCLK
The internal PLLSYSCLK clock, normally used as a source for all clocks, is a divided-down output of the
Main PLL (referred to as the System PLL in some cases) or X1 external clock input, as defined by the
SPLLCKEN bit of the SYSPLLCTL register. There is also a second oscillator that internally generates two
clocks: 32KHZCLK and 10MHZCLK, as shown in the figure above.
The 32KHZCLK, 10MHZCLK, and OSCCLK clocks are used by the master subsystem as possible
sources for the deep sleep clock.
The Cortex-M3 master subsystem operates in one of three modes: run mode, sleep mode, or deep sleep
mode. Refer to Section 1.9
As shown in Figure
enabled and locked) or from the MAIN OSC clock directly (when the PLL is bypassed or turned OFF)
divided by the SYSDIVSEL divider. This PLLSYSCLK is the input clock for the control subsystem and the
M3 system divider (M3SYSDIVSEL) whose output becomes M3SSCLK input to the master subsystem.
During Cortex-M3 normal mode of operation, the master subsystem is clocked by M3SSCLK and all the
master subsystem peripherals when enabled are clocked by M3SSCLK as configured in the RCGCx
registers. An exception is the Watchdog Timer 1 module which is clocked by OSCKCLK directly. The
USBPLL and CAN modules have the option to choose a clock source other than OSCCLK as shown in
Figure 1-11. Refer to the respective sections for more details on USB and CAN clocking configurations.
128
System Control and Interrupts
ASSERT ANY INTERRUPT
NVIC
TO EXIT SLEEP OR DEEP SLEEP
SELECTS TYPE
SLEEPEXIT
OF WAKEUP
SYSCTRL REG
SELECTS BETWEEN SLEEP SLEEPDEEP
AND DEEP SLEEP MODES
ENABLE
CLOCK MODE
M3RUN
M3SLEEP
M3DEEPSLEEP
( CLOCK GATING – RUN )
( CLOCK GATING – SLEEP )
( CLOCK GATING – DEEP SLEEP )
10MHZCLK OSCCLK
MAIN OSC
MISSING
MAIN PLL
CLK DETECT
CLOCKFAIL OSCCLK
for more details on sleep mode and deep sleep mode of operation.
1-11, PLLSYSCLK is either derived from the output of the PLL (when the PLL is
Copyright © 2012–2019, Texas Instruments Incorporated
M3 CPU
INTR
execution of WFI or WFE instr
activates low power modes
FCLK HCLK
ENTER A LOW POWER MODE
DSLPCLKCFG REG
DSOSCSRC DSDIVOVRIDE
32KHZCLK
/1
10MHZCLK M3DSDIVCLK
/2
...
OSCCLK
/16
MCLKREQUEST REG
SYSDIVSEL REG
SYSDIVSEL
SYSPLLSTAT REG
SYSPLLMULT REG
SYSPLLCTL REG
OSCCLK
0 /1
/2
/2
/4
/8
10MHZCLK
1
CLOCKFAIL
CONTROL SUBSYSTEM
SPRUH22I – April 2012 – Revised November 2019
REGISTER
ACCESS
M3SSCLK
M3SSCLK
OSCCLK
M3SSCLK
PERIPH
LOGIC
OSCCLK
CLOCKS
XCLKIN
M3DEEPSLEEP
M3SSDIVSEL REG
OSCCLK
M3SSDIVSEL
XCLKIN
/1
1
M3SSCLK
/2
/4
0
OSCCLK XCLKIN
M3SSCLK
OFF
1
PLLSYSCLK
0
CLPMSTAT REG
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M3CLKENBx
WDOG 1
CAN
1,2
USB + PHY
(OTG)
USBPLLCLK
USB PLL
GPIO_MUX1
IPC
SHARED
RAMS
MSG
RAMS
SHARED
RESOURCES