Mtocipcack Register; Mtocipcack Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

System Control Registers
Bit Field
31 IPC32
30 IPC31
29 IPC30
28 IPC29
27 IPC28
26 IPC27
25 IPC26
24 IPC25
23 IPC24
22 IPC23
21 IPC22
20 IPC21
19 IPC20
18 IPC19
17 IPC18
16 IPC17
15 IPC16
14 IPC15
13 IPC14
12 IPC13
288
System Control and Interrupts
Table 1-180. MTOCIPCACK Register Field Descriptions
Value Description
0 MTOCIPCACK Flag 32. M3 to C28 core IPC flag 32 acknowledge. Writing a '1' to this bit clears the
corresponding bit in MTOCIPCFLG and MTOCIPCSTS to '0'. The status of this bit is not readable
in this register – it is readable in the MTOCIPCFLG and STS registers.
0 MTOCIPCACK Flag 31. M3 to C28 core IPC flag 31 acknowledge. Writing a '1' to this bit clears the
corresponding bit in MTOCIPCFLG and MTOCIPCSTS to '0'. The status of this bit is not readable
in this register – it is readable in the MTOCIPCFLG and STS registers.
0 MTOCIPCACK Flag 30. M3 to C28 core IPC flag 30 acknowledge. Writing a '1' to this bit clears the
corresponding bit in MTOCIPCFLG and MTOCIPCSTS to '0'. The status of this bit is not readable
in this register – it is readable in the MTOCIPCFLG and STS registers.
0 MTOCIPCACK Flag 29. M3 to C28 core IPC flag 29 acknowledge. Writing a '1' to this bit clears the
corresponding bit in MTOCIPCFLG and MTOCIPCSTS to '0'. The status of this bit is not readable
in this register – it is readable in the MTOCIPCFLG and STS registers.
0 MTOCIPCACK Flag 28. M3 to C28 core IPC flag 28 acknowledge. Writing a '1' to this bit clears the
corresponding bit in MTOCIPCFLG and MTOCIPCSTS to '0'. The status of this bit is not readable
in this register – it is readable in the MTOCIPCFLG and STS registers.
0 MTOCIPCACK Flag 27. M3 to C28 core IPC flag 27 acknowledge. Writing a '1' to this bit clears the
corresponding bit in MTOCIPCFLG and MTOCIPCSTS to '0'. The status of this bit is not readable
in this register – it is readable in the MTOCIPCFLG and STS registers.
0 MTOCIPCACK Flag 26. M3 to C28 core IPC flag 26 acknowledge. Writing a '1' to this bit clears the
corresponding bit in MTOCIPCFLG and MTOCIPCSTS to '0'. The status of this bit is not readable
in this register – it is readable in the MTOCIPCFLG and STS registers.
0 MTOCIPCACK Flag 25. M3 to C28 core IPC flag 25 acknowledge. Writing a '1' to this bit clears the
corresponding bit in MTOCIPCFLG and MTOCIPCSTS to '0'. The status of this bit is not readable
in this register – it is readable in the MTOCIPCFLG and STS registers.
0 MTOCIPCACK Flag 24. M3 to C28 core IPC flag 24 acknowledge. Writing a '1' to this bit clears the
corresponding bit in MTOCIPCFLG and MTOCIPCSTS to '0'. The status of this bit is not readable
in this register – it is readable in the MTOCIPCFLG and STS registers.
0 MTOCIPCACK Flag 23. M3 to C28 core IPC flag 23 acknowledge. Writing a '1' to this bit clears the
corresponding bit in MTOCIPCFLG and MTOCIPCSTS to '0'. The status of this bit is not readable
in this register – it is readable in the MTOCIPCFLG and STS registers.
0 MTOCIPCACK Flag 22. M3 to C28 core IPC flag 22 acknowledge. Writing a '1' to this bit clears the
corresponding bit in MTOCIPCFLG and MTOCIPCSTS to '0'. The status of this bit is not readable
in this register – it is readable in the MTOCIPCFLG and STS registers.
0 MTOCIPCACK Flag 21. M3 to C28 core IPC flag 21 acknowledge. Writing a '1' to this bit clears the
corresponding bit in MTOCIPCFLG and MTOCIPCSTS to '0'. The status of this bit is not readable
in this register – it is readable in the MTOCIPCFLG and STS registers.
0 MTOCIPCACK Flag 20. M3 to C28 core IPC flag 20 acknowledge. Writing a '1' to this bit clears the
corresponding bit in MTOCIPCFLG and MTOCIPCSTS to '0'. The status of this bit is not readable
in this register – it is readable in the MTOCIPCFLG and STS registers.
0 MTOCIPCACK Flag 19. M3 to C28 core IPC flag 19 acknowledge. Writing a '1' to this bit clears the
corresponding bit in MTOCIPCFLG and MTOCIPCSTS to '0'. The status of this bit is not readable
in this register – it is readable in the MTOCIPCFLG and STS registers.
0 MTOCIPCACK Flag 18. M3 to C28 core IPC flag 18 acknowledge. Writing a '1' to this bit clears the
corresponding bit in MTOCIPCFLG and MTOCIPCSTS to '0'. The status of this bit is not readable
in this register – it is readable in the MTOCIPCFLG and STS registers.
0 MTOCIPCACK Flag 17. M3 to C28 core IPC flag 17 acknowledge. Writing a '1' to this bit clears the
corresponding bit in MTOCIPCFLG and MTOCIPCSTS to '0'. The status of this bit is not readable
in this register – it is readable in the MTOCIPCFLG and STS registers.
0 MTOCIPCACK Flag 16. M3 to C28 core IPC flag 16 acknowledge. Writing a '1' to this bit clears the
corresponding bit in MTOCIPCFLG and MTOCIPCSTS to '0'. The status of this bit is not readable
in this register – it is readable in the MTOCIPCFLG and STS registers.
0 MTOCIPCACK Flag 15. M3 to C28 core IPC flag 15 acknowledge. Writing a '1' to this bit clears the
corresponding bit in MTOCIPCFLG and MTOCIPCSTS to '0'. The status of this bit is not readable
in this register – it is readable in the MTOCIPCFLG and STS registers.
0 MTOCIPCACK Flag 14. M3 to C28 core IPC flag 14 acknowledge. Writing a '1' to this bit clears the
corresponding bit in MTOCIPCFLG and MTOCIPCSTS to '0'. The status of this bit is not readable
in this register – it is readable in the MTOCIPCFLG and STS registers.
0 MTOCIPCACK Flag 13. M3 to C28 core IPC flag 13 acknowledge. Writing a '1' to this bit clears the
corresponding bit in MTOCIPCFLG and MTOCIPCSTS to '0'. The status of this bit is not readable
in this register – it is readable in the MTOCIPCFLG and STS registers.
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SPRUH22I – April 2012 – Revised November 2019
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